JPH0366867B2 - - Google Patents

Description

Detailed Description of the Invention The present invention uses a counter method that measures the interval between zero crossing points of an FSK signal using a counter and demodulates the original binary signal using the measured value (corresponding to one half of the period of the FSK signal). It relates to an FSK demodulation circuit, and its purpose is to enable the modulation and demodulation circuit to be implemented on an ICI chip, to improve the S/N ratio when demodulating an FSK signal, and to provide highly accurate spacing.

One of the methods commonly used for data communication
There is an FSK communication method. This belongs to the so-called frequency modulation/demodulation method, in which sine waves of different frequencies are transmitted and received in correspondence with digital binary signals "1" and "0".
Used in low-speed modems, etc. An example is shown in FIG. In FIG. 1, A is a digital binary signal, and B is a modulated signal. Conventionally, analog methods such as frequency discrimination and PLL methods have been used as demodulation circuits for FSK communication systems, but these require a large number of individual parts and adjustment points, making it difficult to downsize, maintain long-term stability, and reduce costs. It was hot. In response, a counter method was devised in which the interval between the zero crossing points of the FSK signal (corresponding to 1/2 of the period of the modulated wave) is measured using a counter, and the original binary signal is demodulated based on the magnitude of the value. Most of the demodulation circuits using the counter method are digital circuits, so
Miniaturization through integrated circuits, especially by realizing modulation circuits with digital circuits, has made it possible to improve the size of modulation and demodulation equipment.
It makes it possible to use ICI chips, and along with this, improves reliability, lowers prices, and lowers power consumption.

However, the counter method is sensitive to fluctuations in the zero crossing point caused by noise, and has drawbacks such as increased code distortion when demodulating signals with a small S/N ratio, and even failure to demodulate (performing erroneous demodulation). are doing. A conceivable method to improve this is to use N counters, shift the start and stop of each counter by one zero crossing, and have each counter measure the interval between zero crossings in N consecutive sections. This is because the absolute amount of error due to the fluctuation of zero intersections is the same when measuring the zero intersection interval of N sections and when measuring the zero intersection interval of one section, so when measuring the interval N times, the measured value This is based on the fact that the S/N ratio naturally increases by N times.

The present invention provides an FSK demodulation circuit that can demodulate a signal with a large noise level by using such N counters.

The present invention will be described in detail below based on Examples. First, the counter method will be explained. Figure 3 is a block diagram of a general counter type FSK demodulator, and Figure 4 is a demodulator circuit 5 in Figure 3.
FIG. FIG. 2 shows signal waveforms at each point in FIGS. 3 and 4.
Figure 2 A is the original binary signal, and this is on the transmitting side.
FSK demodulated and sent over the wire. reception
The FSK signal 6 is amplified by the receiving amplifier 1 to the extent that the amplitude does not exceed the clip level, and then only the modulation frequency band of the FSK signal is selected by the bandpass filter 2.The amplitude is limited by the limiter 3 to avoid saturation of the operational amplifier, etc., and then the comparator 4 is converted into a digital binary signal 8. The waveforms of the output 7 of the bandpass filter 2 and the output 8 of the comparator 4 are as shown in FIGS. 2B and 2C. Comparator output 8 is demodulated by demodulation circuit 5 and demodulated signal 9 (second
Figure E) is obtained. Describing the demodulation circuit 5 in more detail with reference to FIG. 4, the comparator output 8 is differentiated by a differentiating circuit in the control circuit 11 and converted into the zero-crossing signal shown in FIG. 2D. This zero-crossing signal is generated when the bandpass filter output (Figure 2B) crosses level 0. Therefore, by measuring the interval of this zero-crossing signal, the frequency of the modulation waveform can be determined. It can be determined from the numerical value whether the original binary signal is "1" or "0". The zero crossing counter 12 measures this zero crossing interval. The demodulation output judgment circuit 13 has a value (hereinafter referred to as a threshold period) corresponding to one-half of the interval of the intermediate frequency of the two types of FSK modulated waves. (Determined experimentally, taking into account the influence of the line, etc.) is set.
The determination circuit 13 determines "1" or "0" based on the magnitude relationship between the output 18 of the counter 12 and the threshold period, and the demodulated output 19 is taken into the demodulated output FF 14 until the next zero crossing interval is measured. Retained. That is, the output 9 of the demodulation circuit remains constant during the zero-crossing interval measurement and can change only at the zero-crossing points. The counter clock 16 is obtained from a clock generation circuit 10, and this signal is also led to a control circuit 11, the control signal being synchronized with the clock signal. The reset signal 17 for starting the counter measurement and the latch signal 15 for loading the demodulated signal obtained from the measured count value into the FF 14 are generated based on the differential signal of the comparator output 8 (Fig. 2D). ing.

As described above, since the counter method performs demodulation through digital processing, it is easy to integrate into an IC, and there is no adjustment and no long-term fluctuations. However, the counter method has the drawback that it is sensitive to fluctuations in the zero crossing point due to noise, and that it is difficult to demodulate signals with a small S/N ratio. For example, if one of the zero crossing points in D in Figure 2, point u, is shifted to the right by dt due to noise, T20 becomes T20 + dt, T21 becomes 21 - dt,
Depending on the magnitude of dt, T20-dt may become smaller than the threshold period, resulting in erroneous demodulation as shown in FIG. 2F.

To solve this problem, the FSK demodulation circuit of the present invention uses N zero-crossing interval measuring counters (N≧2). FIG. 5 shows an embodiment of the present invention that is an improvement on FIG. 4, and is an example when N=4. 112,
113, 114, and 115 are all the same zero-crossing interval measurement counters, but they differ from counter 12 in that they measure four zero-crossing intervals, and each counter starts measurement with a delay of one zero-crossing interval. That is, in FIG. 2D, the counter 112
113 starts measurement from point a, 113 starts measurement from point b, 114 starts measurement from point c, and 114 starts measurement from point d, and measures four sections. (Counter 112 measures the interval marked CNT1, 113 measures CNT2, 114 measures CNT3,
115 measures each section of CNT4. 1
A multiplexer 16 sequentially selects the output of the counter whose measurement has been completed among the outputs 122 to 125 of the four counters. The start of counter measurement and selection of counter output are controlled by reset signals 117 to 120 and selection signal 121 output from control circuit 111. Point u in Figure 2 D is on the right
Let's take again the example from earlier where dt is shifted. In Figure 5, each counter is considered to be measuring the average of four zero-crossing intervals, so the measured value is (T16+T17+T18+T19)/4→
(T17+T18+T19+T20+dt)/4→(T18+
T19+T20+T21)/4→(T19+T20+T21+
T22)/4→(T20+T21+T22+T23)/4→
(T21-dt+T22+T23+T24)/4, and the error is reduced to dt/4. That is, the S/N is improved four times compared to the circuit shown in FIG. Generally, if N counters are used, the S/N ratio will be improved by N times, and the weakness of the counter method against noise can be eliminated by the above method.

However, the counter method still has major drawbacks due to the method itself. The disadvantage is that the demodulated output can only change at zero crossing points, which increases single point distortion. This will be explained in FIG. In the description, a case will be considered in which there is one zero-crossing interval measurement counter. Regarding single point distortion, the number of counters does not matter, and the same argument holds true even when N counters are used, although there are some differences. Let A in FIG. 6 be the original binary signal on the transmitting side. Here, if the modulation speed (baud rate) is B, the time length T of 1 bit of the original binary signal is T = 1/B
becomes. FIG. 6B is an FSK signal obtained by modulating the original binary signal A and received through the line, and C is its zero crossing signal. Figure 2D shows the demodulated signal obtained by comparing the magnitude of the zero-crossing interval value and the threshold period.
Te corresponds. Time T2 from zero intersection b to c
is smaller than the threshold period and outputs 0 at point c as the demodulated output for T2. Similarly, a demodulated output of 1 for T3 is output at point d, a demodulated output of 1 for T7 is outputted at point h, and a demodulated output of 0 for T8 is outputted at point i. Since the change in the demodulated output is limited to the zero crossing point in this way, the delay time from the change point of the original binary signal to the change point of the demodulated output is not constant, and the time length of one bit of the demodulated output changes. Put it away. In the example in Figure 6, for the change point x from 0 to 1, the demodulated output changes at point d with a delay of △x, and for the change point y from 1 to 0, the demodulated output changes at point i with a delay of △y. T=T+(Δy−Δx). When the maximum and minimum values of Te are Temax and Temin, (Temax-T)/T and (Temin-
T)/T is called single point distortion, and another drawback of the counter method was that this single point distortion was large.

FIG. 7 is a block diagram showing another embodiment in which the problems in the embodiment of FIG. 6 are further improved. A delay compensation circuit is provided to delay the demodulated output, and the original 2
By reducing the variation in delay time from the change point of the value signal to the demodulated output, (△y-
This is a method of reducing single point distortion by bringing Δx) close to 0, and FIG. 6E shows an ideal demodulated output with a delay. The constant delay amount D from the change point of the original binary signal to the change point of the demodulated output is determined as the maximum value of Δx (Δy) in all cases shown in FIG. 6D. At each zero crossing point, the zero crossing interval from the previous zero crossing point is measured, and a demodulated signal is obtained by comparing the magnitude relationship with the threshold period.
The zero-crossing interval of this demodulated signal from the previous zero crossing point is measured, and the demodulated signal is obtained by comparing the magnitude relationship with the threshold period. In different cases, ie, when changing from 0 to 1 or from 1 to 0, the demodulated signal is not output immediately at the zero crossing, but after a suitable delay is applied. The amount of delay applied at the inverted zero crossing point of the demodulated signal, for example, point d, is calculated by predicting the conversion point x of the original binary signal and subtracting the delay time Δx from x to d from the constant delay amount D (D- Δx). Change prediction point x to d of original binary signal
Time to point △x is time from x to point c △xc
and the time △cd from point c to point d, and △
x=△xc+△cd.

Here, Δcd=T3, and Δxc is determined by the values of T2 and T3, the characteristics of the line bandpass filter, etc. Therefore, by experimentally measuring the characteristics of the line, bandpass filter, etc., Δx can be determined from the values of T2 and T3, and the compensated delay amount ΔD=D−Δx.

FIG. 7 shows an FSK demodulation circuit based on the principle described above. The control circuit 111, the zero crossing interval measurement counters 112 to 115, and the multiplexer 116 are the fifth
Same as the figure. 201 and 212 are registers, the clock 15 of which is obtained from a zero crossing signal. Therefore, 201 stores the measured value of the zero crossing interval at the current zero crossing, and 202 stores the measured value at the previous zero crossing. 13 is a demodulation output determination circuit, which generates a demodulation signal 19 from the output of the register 201, and the demodulation signal 19 is a demodulation output.
It is led to the D input terminal of FF14. If the demodulated signal 19 is different from the previous demodulated output, the demodulated signal is not immediately taken into the FF 14, and the demodulated signal 201,
After being delayed by the delay compensation circuit 203 by the delay time determined from the values of the outputs 204 and 205 of the register 202, the latch pulse 206 causes the FF14
be taken in. The delay compensation circuit 203 can be easily constructed by using a ROM that receives the register outputs 204 and 205 as input and outputs the delay time.

By applying an appropriate delay to the demodulated signal and outputting it as described above, the FSK demodulation circuit shown in FIG. 7 can obtain a demodulated output with extremely small single point distortion.

Furthermore, in the FSK demodulation circuit according to the present invention, the threshold period storage memory 301 and the delay amount storage memory in the delay compensation circuit 203 are PROM.
(programable read only memory), a general-purpose FSK demodulation circuit can be constructed.
This is particularly effective when the FSK demodulation circuit according to the present invention is made into a single chip IC, and by rewriting the PROM section, one IC can be used as an FSK demodulation circuit for any frequency.

Furthermore, the above memory can be changed to RAM (Random
(access mamory), and has an optimal numerical value determination circuit to determine the contents of RAM. Before receiving the FSK signal, a test waveform is received, and from the test waveform, the optimal numerical value determination circuit determines the value to be stored in RAM. A complete general-purpose FSK demodulation circuit can be constructed by providing a mechanism to determine and store the
It is particularly effective for chip IC implementation. By measuring the line characteristics in addition to the frequency used from the test waveform, the threshold period and delay amount are set optimally for the current communication state, enabling high-performance demodulation.

[Brief explanation of drawings]

FIGS. 1A and 1B are diagrams showing the relationship between the original binary signal and the FSK signal. In FIG. 2, A to F are diagrams showing an example of demodulating an FSK signal and waveforms of each part of the demodulation circuit. FIG. 3 is a block diagram of an FSK demodulator using a counting method. FIG. 4 is a conventional circuit configuration diagram of the demodulation circuit 5 in the demodulation device shown in FIG. FIG. 5 is a block diagram of an FSK demodulation circuit according to the present invention. FIGS. 6A to 6E are according to the present invention.
FIG. 3 is a diagram for explaining another configuration diagram of the FSK demodulation circuit. FIG. 7 is another configuration diagram of the FSK demodulation circuit according to the present invention. 1...Reception amplifier, 2...Band bus filter, 3...Limiter, 4...Comparator, 5...
...Demodulation circuit, 10...Clock generation circuit, 11...
...Control circuit, 12...Zero crossing interval measurement counter,
13...Demodulation output determination circuit, 14...Demodulation output
FF, 111...control circuit, 112-115...
Zero crossing interval measurement counter, 116... Multiplexer, 201... New zero crossing interval storage register, 2
02... Old zero crossing interval storage register, 203...
Delay compensation circuit.

Claims (1)

[Claims] 1. A detection circuit that detects zero crossing points from an FSK signal consisting of a series of signals of two types of frequencies modulated corresponding to the original binary signal, and consecutive N+1 (N≧2) detected by the detection circuit. ) a plurality of zero-crossing interval measurement counters that perform a counting operation during the zero-crossing interval N section formed between the zero-crossing points;
In response to the detection of the zero crossing by the detection circuit, the plurality of zero crossing interval measuring counters sequentially start counting operations, and a selection signal is output for selecting the zero crossing interval measuring counter that has completed the counting operation. a control circuit; a selection circuit that selects and outputs a count result value output from a desired zero-crossing interval measuring counter from among the outputs of the plurality of zero-crossing interval measuring counters according to the selection signal; and the selecting circuit; The value of "1" or ".0" determined based on the value of the count result selected and output from
1. An FSK demodulation circuit comprising a demodulation output holding circuit for demodulating a value signal.