JPH036735U - - Google Patents
Info
- Publication number
- JPH036735U JPH036735U JP6687889U JP6687889U JPH036735U JP H036735 U JPH036735 U JP H036735U JP 6687889 U JP6687889 U JP 6687889U JP 6687889 U JP6687889 U JP 6687889U JP H036735 U JPH036735 U JP H036735U
- Authority
- JP
- Japan
- Prior art keywords
- digit
- decimal
- result
- multiplier
- addition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000012795 verification Methods 0.000 description 1
Description
第１図は本考案の一実施例に係わる１０進乗算
器の誤り検出回路１０の構成を１０進乗算器２０
と共に示すブロツク図、第２図乃至第４図は第１
図の各部の処理内容を具体的な数値を挙げつつ説
明するための概念図である。
１１……被乗数の各桁加算手段、１２……乗算
の各桁加算手段、１３……乗算及び各桁加算手段
、１４……積の各桁加算手段、１５……照合手段
。
FIG. 1 shows the configuration of a decimal multiplier error detection circuit 10 according to an embodiment of the present invention.
The block diagrams shown together with Figures 2 to 4 are
FIG. 3 is a conceptual diagram for explaining the processing contents of each part in the diagram while citing specific numerical values. 11...Means for adding each digit of the multiplicand, 12...Means for adding each digit of multiplication, 13...Means for multiplying and adding each digit, 14...Means for adding each digit of product, 15...Verification means.
Claims (1)
算されたこれらの積のそれぞれをｎ桁（ｎは自然
数）ごとに区切り、この区切られたｎ桁の１０進
数どうしを加算結果がｎ桁の１０進数になるまで
加算する被乗数、乗数及び積の各桁加算手段と、 前記被乗数の各桁加算手段の加算結果及び乗数
の各桁加算手段の加算結果どうしを乗算し、この
乗算結果がｎ桁以下の１０進数であればこれをそ
のまま演算結果とし、この乗算結果がｎ桁を越え
る１０進数であればをこれをｎ桁ごとに区切りこ
の区切られたｎ桁の１０進数どうしを加算結果が
ｎ桁の１０進数になるまで加算して演算結果とす
る乗算及び各桁加算手段と、 この乗算及び各桁加算手段の加算結果と前記積
の各桁加算手段の加算結果とを照合し、照合不一
致の場合には誤り検出信号を出力する照合手段と
を備えたことを特徴とする１０進乗算器の誤り検
出回路。[Claims for Utility Model Registration] A decimal multiplicand, a multiplier, and each of these products multiplied by a decimal multiplier are separated into n-digit units (n is a natural number), and the separated n-digit decimal numbers are means for adding each digit of the multiplicand, multiplier, and product until the addition result becomes an n-digit decimal number, and multiplying the addition result of each digit addition means of the multiplicand and the addition result of each digit addition means of the multiplier. , if the result of this multiplication is a decimal number with n digits or less, it is used as the operation result, and if the result of this multiplication is a decimal number with more than n digits, it is divided into n-digit units and the divided n-digit 10 is used. A multiplication and each-digit addition means for adding base numbers together until the result becomes an n-digit decimal number, and an addition result of this multiplication and each-digit addition means and an addition result of the product of each digit addition means. 1. An error detection circuit for a decimal multiplier, characterized in that the error detection circuit for a decimal multiplier is characterized in that it is provided with a matching means for comparing the numbers and outputting an error detection signal in the case of mismatch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6687889U JPH036735U (en) | 1989-06-07 | 1989-06-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6687889U JPH036735U (en) | 1989-06-07 | 1989-06-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH036735U true JPH036735U (en) | 1991-01-23 |
Family
ID=31599963
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6687889U Pending JPH036735U (en) | 1989-06-07 | 1989-06-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH036735U (en) |
-
1989
- 1989-06-07 JP JP6687889U patent/JPH036735U/ja active Pending
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