JPH0367396B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a video signal processing device applied to a receiving side when video signals are transmitted at low speed or intermittently.

For example, when transmitting a video signal through a narrowband transmission path such as a telephone line, the video signal is transmitted at low speed, and the receiving side stores this video signal in memory, magnetic disk recorder, etc. ,
A normal still image can be monitored by reading or playing back at normal speed. Similar processing is performed when transmitting image-generated data by a computer.

During the transmission of such video signals, or when only a portion of one frame exists for some reason, a normal monitor receiver will lose synchronization and the monitor will not work properly. can't do it. An object of the present invention is to realize a video signal processing device that makes it possible to normally monitor a portion of the existing video even in such a case. The present invention prevents synchronization disturbances by forming a synchronization signal that is synchronized with a video signal that is only partially present.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, reference numeral 1 indicates an input terminal to which color video data transmitted at low speed by analog or digital is supplied. This color video data is transferred to frame memory 3 via interface 2.
written to. Color video data also includes a synchronization signal and a burst signal. Further, a memory control circuit 4 is provided in association with the frame memory 3, and a clock pulse from a clock oscillator 5 is transmitted to the memory control circuit 4.
A write address signal, a read address signal, and write and read control signals are formed.

The received color video data is written into the frame memory 3 in the same order. The address signal during this writing is of a low frequency that is synchronized with the received video data. Further, the contents of the frame memory 3 are sequentially read out by a read address signal having a frequency corresponding to a regular sampling frequency, for example, 4sc (sc: color subcarrier frequency).

The readout output of this frame memory 3 is D/A
After being converted into an analog color video signal _S1 by the converter 6, one input terminal 8A of the switching circuit 7
is supplied to The output terminal 8C of this switching circuit 7 is led out as an output terminal 9, and the color video signal _S2 appearing at this output terminal 9 is supplied to a color monitor receiver.

Further, the color video signal S ₁ appearing at the output of the D/A converter 6 is supplied to a sync separation circuit 10 , where the horizontal sync signal PHD is separated and supplied as one input to an AND gate 11 . A switching pulse P _S is supplied as the other input of this AND gate 11 . The switching pulse P _S is generated in the memory control circuit 4 and corresponds to the amount of color video data written in the frame memory 3. As described above, the received color video data is written into the frame memory 3, but if the amount of writing does not reach one frame, the write address counter stops in the middle of one frame. By detecting this, frame memory 3
When reading color video data from P S , the switching pulse P _S has a high level in the section where color video data exists and a low level in the section where color video data does not exist.
can be formed.

The output of this AND gate 11 is supplied to the synchronizing signal generating circuit 12 as its reset pulse.
The synchronization signal generation circuit 12 performs processing such as frequency division of the clock pulse from the clock oscillator 5 to generate a composite synchronization signal SYNC (i.e., a signal in which the horizontal synchronization signal, vertical synchronization signal, and equalization pulse are made into a standard signal waveform). ) occurs. This composite synchronization signal SYNC is synchronized with the horizontal synchronization signal PHD appearing at the output of the AND gate 11. Furthermore,
A burst signal generation circuit 13 that generates a burst signal SB is provided. The burst signal SB is
It is formed by dividing the clock pulse, and has a predetermined phase relationship with respect to the horizontal synchronizing signal generated by the synchronizing signal generating circuit 12.

This composite synchronization signal SYNC and the burst signal SB are combined by an adder circuit 14, and this adder circuit 1
4 is supplied to the other input terminal 8B of the switching circuit 7. The switching circuit 7 is controlled by a switching pulse P _S , and the input terminal 8A and the output terminal 8C are connected when the switching pulse _PS is at a high level, and the input terminals 8B and 8C are connected when the switching pulse P _S is at a low level. 8C is connected.

In the above configuration, in the frame memory 3,
The operation when only part of the video data in one frame is written will be explained.

FIG. 2A shows the color video signal S ₁ read out from the frame memory 3 and emerging from the D/A converter 6. In FIG. 2, illustration of the carrier color signal component is omitted for simplicity. This color video signal S ₁ exists at a timing indicated by t ₁ ,
After that, it does not exist.

By supplying this color video signal _S1 to the synchronization separation circuit 10, a horizontal synchronization signal PHD as shown in FIG. 2B is separated. This horizontal sync signal PHD
A signal consisting of the composite synchronization signal SYNC and the burst signal SB shown in FIG.
arises from. Then, at timing t ₁ ,
A switching pulse P _S shown in FIG. 2E that falls from a high level to a low level is generated. At the fall of this switching pulse P _S , the state in which the input terminal 8A and the output terminal 8C of the switching circuit 7 are connected is switched to the state in which the input terminal 8B and the output terminal 8C are connected. Therefore, the color video signal S ₂ shown in FIG. 2D (the carrier color signal is omitted) appears at the output terminal 9. As is clear from Figure 2B,
Although the horizontal synchronization signal PHD no longer exists after timing _t1 , the synchronization signal generation circuit 12 continues to generate the composite synchronization signal SYNC of the phase up to that point.

As understood from the description of one embodiment above,
According to this invention, even in sections where no video signal is transmitted, a composite synchronization signal synchronized with this video signal exists, so that a portion of the video received by a normal monitor receiver can be displayed. Can be played normally. In addition, in the case of color video signals,
By adding not only the composite synchronization signal but also the burst signal, it is possible to prevent malfunctions in which some of the received images are not colored. In other words, if a burst signal is not present, the color killer circuit in the color monitor receiver will operate, and due to its operating time constant, the color killer operation will not be canceled immediately even when a color video signal is present again. .

Further, in the embodiment of the present invention described above, the input to the synchronous separation circuit 10 is taken from the output of the D/A converter 6, but unlike this, the input may be taken from the output side of the switching circuit 7. In this case, the synchronization signal generation circuit 1 is activated by the horizontal synchronization signal separated from the color video signal _S2 shown in FIG.
2 is reset.

Furthermore, as the synchronization signal and burst signal supplied to the other input terminal 8B of the switching circuit 7, a DC potential of an appropriate level is added to the video section, and the received color video signal is applied to the section where no color video signal is present. It may also be displayed in gray.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a waveform diagram used to explain the operation of the embodiment of the invention. 1...Input terminal, 3...Frame memory, 6
...D/A converter, 7...Switching circuit, 9...
Output terminal, 10... synchronous separation circuit, 12... synchronous signal generation circuit.

Claims (1)

[Claims] 1. A memory circuit that stores video signals and synchronization signals that are transmitted at low speed or intermittently, and that generates a low-frequency write signal synchronized with the video signals and that has a standard sampling frequency for display. a memory control circuit that generates a corresponding read signal; a synchronization signal separation circuit that separates the synchronization signal using the output signal from the memory circuit; a synchronization signal generation circuit for generating a composite synchronization signal synchronized with the signal; and a synchronization signal generation circuit for detecting a position where the video signal and synchronization signal stored in the memory circuit cease to exist within one field or one frame, and generating a detection signal. a switching circuit that switches between the video signal taken out from the memory circuit at the position and the composite synchronization signal from the synchronization signal generation circuit based on the detection signal and leads it to a monitor output terminal; A video signal processing device comprising: