JPH0367432U - - Google Patents

Info

Publication number
JPH0367432U
JPH0367432U JP1989128972U JP12897289U JPH0367432U JP H0367432 U JPH0367432 U JP H0367432U JP 1989128972 U JP1989128972 U JP 1989128972U JP 12897289 U JP12897289 U JP 12897289U JP H0367432 U JPH0367432 U JP H0367432U
Authority
JP
Japan
Prior art keywords
semiconductor device
cell
transistor
terminals
width direction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1989128972U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989128972U priority Critical patent/JPH0367432U/ja
Publication of JPH0367432U publication Critical patent/JPH0367432U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5453—Dispositions of bond wires connecting between multiple bond pads on a chip, e.g. daisy chain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第１図はこの考案の一実施例による半導体装置
の構成図、第２図は従来の半導体装置の構成図、
第３図は従来の他の半導体装置の構成図である。 １……トランジスタチツプ、２……トランジス
タセル部、３……ボンデイングパツド、４……抵
抗、５……入出力ワイヤ。なお、図中同一符号は
同一又は相当部分を示す。

Claims (1)

  1. 【実用新案登録請求の範囲】 幅広のトランジスタセルと該セルに対応してそ
    の幅方向に複数個設けられたボンデイングパツド
    とを具備するトランジスタチツプを有する半導体
    装置において、 前記トランジスタセルと上記ボンデイングパツ
    ドの間に挿入された抵抗を備えたことを特徴とす
    る半導体装置。
JP1989128972U 1989-11-02 1989-11-02 Pending JPH0367432U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989128972U JPH0367432U (ja) 1989-11-02 1989-11-02

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989128972U JPH0367432U (ja) 1989-11-02 1989-11-02

Publications (1)

Publication Number Publication Date
JPH0367432U true JPH0367432U (ja) 1991-07-01

Family

ID=31676641

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989128972U Pending JPH0367432U (ja) 1989-11-02 1989-11-02

Country Status (1)

Country Link
JP (1) JPH0367432U (ja)

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