JPH036754A - Data transfer control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Conventional technology Problems to be solved by the invention Means for solving the problems Function Example 1 Correspondence between the example and FIG. 1 ■ , Configuration and operation of the embodiment ■ Summary of the embodiment ■ 1 Modifications of the invention Effects of the invention (Summary) Transfer of data in units of programs between an extended memory composed of semiconductor memory and a main storage device A data transfer control method in which data transfer is performed via a control device Aiming at reducing the burden on the processor, the data transfer control method includes a processor, a main storage device, an extended storage device, and a storage control device. Start reception is performed by means for accepting a start request supplied from the processor prior to unit data transfer, and start reception is performed by reading the transfer content data on the main storage device according to the start request received by the means, and performing this transfer. request generating means for generating a read request or a write request in units of data length that can be transferred at one time based on content data and outputting it to the main storage device, and responding to the request output from the request generating means and a transfer data amount calculation means that calculates the data length of the transferred request and sends a request generation instruction to the request generation means until the data length corresponds to the data length in block units, The device is configured to repeatedly send requests to the main storage device.

(Industrial Application Field) The present invention relates to a data transfer control method in which data is transferred in blocks between an extended memory configured with a semiconductor memory and a main storage device via a storage control device. .

[Prior Art] A main memory in a computer system is composed of a semiconductor memory that can be accessed at high speed, and can be directly addressed by software. On the other hand, auxiliary storage devices are used to supplement the limited capacity of main storage devices.

This auxiliary storage device is generally composed of a disk device, etc., but recently, with the increase in capacity and cost reduction of semiconductor memory, a part of it is composed of semiconductor memory, which has a large capacity. Moreover, it can be realized as a high-speed extended storage device.

FIG. 5 shows the overall configuration of the computer system.

In FIG. 5, 511 is a central processing unit (CPU) that performs processing such as program execution and data calculation.

521 is an upper storage unit (MSU) composed of semiconductor memory.
), and can be directly read and written by the central processing unit 511 via a storage control device 541, which will be described later. 531
is an expansion memory composed of semiconductor memory. When the central processing unit 511 accesses data in the extended memory 531, it transfers it to the mutual storage device 521 and accesses the transferred data.

551 is a channel control device ff (CHP), which controls the channel device (CH) 56 when accessing the input/output device.
1,571 etc.

A disk device 563 is connected to the channel device 561, and access to the disk device 563 is performed via the channel device 561. A display connected to the channel device 571 and the like.

The same applies when accessing a printer or the like (not shown). Further, 541 is a storage control unit (MCU), and data and instructions are exchanged between each component device via this storage control unit 541.

In the computer system described above, the extended memory 531 as a substitute for the auxiliary storage device is composed of a semiconductor memory, and therefore can be accessed much faster than the disk device 563.

Therefore, frequently accessed data can be stored in this expanded memory 5.
By storing the information in 31, it becomes possible to increase the processing speed of the entire computer system.

For example, if the extended memory 531 is used in so-called paging, which exchanges data in blocks (for example, in units of 4 bytes) between the main storage device 521 and the auxiliary storage device, the time required for paging can be shortened and the processing capacity can be increased. It becomes possible to improve. In this case, the processor that controls paging (the central processing unit 511 or a paging-dedicated processor (not shown)) divides the paging block into data length units (for example, 8 bytes) that can be transferred at a time, and The request is sent to the storage system '4B device 541. Storage control device 541
transfers 8 bytes of data each time it accepts this request. This data transfer operation is repeated until the paging target block is completed.

[Problem to be solved by the invention]

By the way, in the conventional method described above, there is a problem in that it is necessary to output a request in units of data length that can be transferred by the processor, which places a heavy burden on the processor.

In particular, since the extended memory 531 is composed of semiconductor memory, it is capable of high-speed operation, and the frequency of requests that the processor outputs increases each time, and the burden that this processor requires to output requests for data transfer cannot be ignored. It becomes a thing.

The present invention was created with these points in mind, and it is an object of the present invention to provide a data transfer control system that reduces the burden on the processor.

[Means to solve the problem]

FIG. 1 is a principle block diagram of the data transfer control system of the present invention.

In the figure, a data transfer control system includes a processor 111, a main storage device 113, an expanded storage device 115, and a storage control device 117, and performs data transfer in blocks between the main storage device 13 and the expanded storage device 115. In the storage control device 117, the startup reception means 121 receives the startup request supplied from the processor III prior to data transfer in units of blocks. If the transfer content data on the device 113 is read and data transfer is possible between the main storage device 113 and the extended storage device 115 based on this transfer content data, the data can be transferred at one time. Request generating means 13 that generates a read request or a write request in units of length and outputs it to the main storage device 113
1, and transfer data that calculates the data length of the transferred request according to the request output from the request generation means 131, and sends a request generation instruction to the request generation means 131 until it corresponds to the data division in blocks. The storage controller 117 is configured to repeatedly send requests to the main storage device 113 from the storage control device 117 in response to a startup request.

[For production]

The data transfer control method of the present invention includes a processor 111, a main storage device 113, an extended storage device 115, and a storage control device 1.
17, and data transfer is performed in units of blocks between the main storage device 113 and the extended storage device 115 via the storage control device 117.

Processor 111 prior to data transfer in blocks
When a startup request is supplied to the storage control device 117 from the storage controller 117, the startup request is accepted by means 121.

The request generating means 131 reads the transfer content data on the main storage device 113 based on the received activation request, and based on this transfer content data, data can be transferred between the main storage device 113 and the extended storage device 115. In this case, a read request or a write request is generated in units of data length that can be transferred at one time. This request generation operation is repeated until it corresponds to data division in blocks in accordance with a request generation instruction supplied from the transfer data landscape calculation means 141 that calculates the amount of transfer data, and the generated request is transferred to the main memory. Sent to 113.

In the present invention, the activation request is executed by the storage control device 11.
7, if data transfer is possible between the main storage device 113 and the extended storage device 115 based on the transfer content data on the main storage device 113, the data that can be transferred at one time. The load on the processor can be reduced by repeatedly generating read requests or write requests corresponding to the block-by-block data division and sending them to the main storage device 113.

[Example] Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of an embodiment to which the data transfer control method of the present invention is applied. Further, FIG. 3 shows the detailed configuration of the data transfer request control section of the embodiment.

Here, the correspondence between I and 1 will be shown between the embodiment of the present invention and FIG.

Processor 111 corresponds to central processing unit 211.

The main storage device 113 corresponds to the main storage device 221.

The extended storage device 115 corresponds to the extended memory 231.

The storage control device 117 corresponds to the storage control device 241.

The activation reception means 121 corresponds to the activation register 3I3.

The request generation means 131 includes the state machine control unit 3
11. Management information storage unit 315. Extended memory address register 317. Request generation register 321. MSUS
This corresponds to the door address counter 31.

The transfer data amount calculation means 141 includes a data length all O detection section 319. This corresponds to the data length counter section 341.

Examples of the present invention will be described below assuming that the correspondence relationship as described above exists.

■The computer system shown in Figure 2 has a central processing unit (CP).
U) 211. Main storage unit (MSU) 22 units, expansion memory 231 units. It is equipped with 24 storage control units (MCU) and 251 channel control units (CHP). Central processing unit 2
11. Main storage device 221, extended memory 231. The channel control device 251 is connected to the storage control device 241, and data and instructions are exchanged via this storage control device 241.

In this embodiment, the main storage device 221 and the expansion memory 231
We focused on data transfer operations between disk devices and displays that are not directly related to this operation.

Keyboard 5 Printer etc. have been omitted.

The storage control device 241 also has interface registers 261, 263, 265 . Selector 267, priority control unit 269. Access pipeline 271. Access source interface 273. Expansion memory control unit 275.
MSU control section 277, transfer data section 283. A data transfer request control section 291 is provided.

Interface registers 261, 263, and 265 are for receiving requests.

A request sent from the central processing unit 211 to the storage control device 241 is temporarily held in the interface register 261, and the request is accepted. Similarly, a request from the channel control device 251 is accepted by the interface register 263, and a request from the data transfer request control unit 291 (details will be described later) is accepted by the interface register 265.

The priority control unit 269 monitors these interface registers 261 to 265, and controls the selector 267 to select the request with the highest priority when requests are received at the same time. Selector 2
The request selected by 67 is supplied to the access pipeline 271 and the MSU control unit 277.

The access pipeline 271 also includes an extended memory 27
5 is a shift register for sequentially holding requests and supplying data to each circuit (not shown) in the storage control device 241. P in the access vibe line 271 (1+Pl+..., P8...
Each is a register that holds a request, and by connecting each register, a shift register is configured and an access pipeline 271 is realized.

For example, from the selector 267 to the access pipeline 27
The request supplied to P1 is once stored in register P0 and then supplied to extended memory control unit 275. Also,
This request is sequentially shifted to register P and subsequent registers, and after being stored in register P, for example, is supplied to the access source interface 273. In response to the supply of the request, the access source interface 273 notifies the access source of information such as that the processing corresponding to the request has been completed.

The MSU IIL control unit 277 controls the storage control device 241
It sends a request to the main storage device 221 from the main storage device 221, receives request processing information sent from the main storage device 221 to the storage control device 241, and causes fetch data to be set in the transfer data section 283. It is for the purpose of All requests output from the selector 267 are supplied to this MSU control unit 277, but only requests related to the main storage device 221 are sent.

Further, the extended memory control unit 275 starts its operation in response to a request to start a transfer processing operation on the access pipeline 271, and controls reading and writing of data in the extended memory 231. When a block of data is transferred between the main storage device 221 and the extended memory 231, data read from one is temporarily stored in the transfer data section 283, and then transferred to the other.

The data transfer request control unit 291 controls the main storage device 2
21, a request to start a transfer processing operation to the extended memory control unit 275, and a request to the main storage device 221 when transferring a block of data.
Create and output a request (fetch request, store request) that instructs to read or write data. For example, a request to the main storage device 221 has a data length of 8 bytes or 64 bytes for reading, and a data length of 8 bytes for writing.
These requests are bytes or 16 bytes, and the output of these requests is repeated until the data length of the entire block is satisfied.

Request control unit 2 for data transfer based on startup request
91 and the extended memory control unit 275 start operation, and the data transfer request control unit 291 reads the transfer contents from the main storage device 221. For the read transfer contents,
For example, when transferring a block of data from the main storage device 221 to the extended memory 231, the data transfer request control unit 29I outputs a request to start the transfer processing operation for the extended memory control unit 275, and the extended memory control unit 275 accesses This request is accepted from the pipeline 271 and the transfer processing operation is started. Thereafter, when the data transfer request control section 291 receives data transfer enable information from the extended memory control section 275, the fetch request output from the data transfer request control section 291 is sent to the interface register 265. selector 267
and MSU! ! I control section 277 spine section 277 storage device 221
sent to. Thereafter, this request generation is repeated until the data length of the entire block is satisfied, and the data read from the main storage device 221 in response to each request is sequentially stored in the transfer data section 283. The extended memory control section 275 monitors the amount of data accumulated in the transfer data section 283, and when it reaches a predetermined amount, it sequentially reads the data and sends it to the extended memory 231 until the data length of the entire block is satisfied.

On the other hand, when transferring a block of data from the extended memory 231 to the main storage device 221, the data transfer request control unit 291 outputs a request to start the transfer processing operation for the extended memory control unit 275, and the extended memory control unit 27
5 starts the transfer processing operation. Expanded memory control unit 275
reads data from the extended memory 231 and stores it in the transfer data section 283. The extended memory control unit 275 repeats this operation thereafter until the data length of the entire block is satisfied. When the data transfer request control unit 291 receives the data transfer enable information from the extended memory control unit 275, the store request output from the data transfer request control unit 291 is sent to the main storage device 221. Thereafter, the output of this store request is repeated until the data length of the entire block is satisfied.

FIG. 3 shows a detailed configuration of the data transfer request control section 291.

In FIG. 3, the data transfer request control unit 291
is the state machine control unit 311. Startup register 313
．． Management information storage unit 315. Extended memory address register 317. Data length all 0 detection unit 319. Request generation register 321゜MSU address counter section 331.
The data length counter section 341 is also provided.

The state machine control unit 311 has a management information storage unit 315.
The entire data transfer request control unit 291 is controlled based on timing information (state information) for request generation stored in the data transfer request control unit 291 .

The activation register 313 is for the state machine control unit 311 to recognize the supply of a activation request when the expansion memory control unit 275 is supplied with this activation request. For example, the operation code included in the activation request supplied to the extended memory control unit 275 is copied to the activation register 313, and the state machine control unit 311 decodes this operation code and recognizes acceptance of the activation request.

Further, after receiving the activation request, the extended memory address register 317 outputs a request for the data transfer request control unit 291 to read the transfer content data on the main storage device 221, and the read data This is used to hold the address of the extended memory 231 included in the .

Furthermore, like the extended memory address register 317, the MSU address counter unit 331 holds the MSU address included in the transfer content data as an initial value, and thereafter transfers the entire block of data in units of several bytes that can be transferred at once. This is to calculate the address of the main memory 221 where this number is to be read and written.

The MSU address counter section 331 includes a selector 333,
It consists of a register 335 and an adder 337. After the address of the main storage device 221 included in the transfer content data is stored as an initial value in the register 335, n (the number of bytes of data that can be transferred at one time) is added to this initial value, and this addition result is sent to the selector. 333 and stored in the register 335 again. Similarly, register 3
By adding n to the stored value of 35, the main entry (, f
The address value of the l device 221 is updated.

The data length counter section 341 includes the extended memory address register 317. Similar to the MSU address counter unit 331, the transfer data length included in the transfer content data is held as an initial value, and when data in units of blocks is subsequently transferred in units of several bytes, the remaining bytes of data that have not yet been transferred are It is for counting numbers.

The data length counter section 341 includes a selector 343, a register 345, and a subtracter 347. The transfer data length (the number of bytes of the transfer block, for example 4 bytes) included in the transfer content data is set to register 3 as an initial value.
After being stored in 45, n is subtracted from this initial value,
This subtraction result is transferred to the register 3 again via the selector 343.
45. Similarly, by sequentially subtracting n from the value stored in the register 345, the number of remaining hides of data to be transferred is updated.

The data length all O detection unit 319 detects that the count value by the data length counter unit 341 has reached “0”, and notifies the state machine control unit 311 of the detection of this count value “0”. .

The state machine control unit 311 recognizes the end of data transfer for the entire block based on the notification from the data length all 0 detection unit 319.

The request generation register 321 also handles requests to read transfer content data and the extended memory control unit 27 that requires the address of the extended memory address register 317.
5, a request to start the transfer processing operation, as well as a fetch request or store request for the main storage device 221 in units of several bytes that can be transferred at a time for transfer, and to send it to the interface register 265. . The state machine control unit 311 controls the main storage device 221 according to the count value by the data length counter unit 341.
Set a request for any number of bytes of data to be sent to.

For example, when the request to be sent to the main storage device 221 is a fetch request, if the number of bytes of the untransferred data is 64 or more, the number of bytes of the transferred data is set to 64; In some cases, the number of hides of transfer data is set to eight. The state machine control unit 311 sets the number of transfer bytes to the value n for addition or subtraction in the MSUS address counter 31 and data length counter unit 341. In addition, the state machine control unit 311 generates an operation code or an expansion memory control unit 27 that instructs the main storage device 221 to write or read data of the number of transferred hides.
The operation code of the start request for the transfer processing operation No. 5 is output and stored in a part of the request generation register 321.

In addition, when storing a request to start the transfer processing operation of the extended memory control unit 275 in other parts of the request generation register 321, the address and data length counter of the extended memory address register 317 required by the request are stored in other parts of the request generation register 321. The transfer data length of the section 341 is stored, and when storing a fetch request or a store request to be sent to the main storage device 221 for transfer, the M
The address of the SUS address counter 31 is stored,
It is output from the data transfer request system fI 11 section 291 together with the stored operation code of each request.

The fourth diagram shows the operation procedure for request generation in the data transfer request control unit 291. Hereinafter, the unit of operation by the state machine control unit 311 will be referred to as a state.
The operation will be explained while taking correspondence with each state.

■Stop state: The state machine control unit 31 judges whether there is a start request or not, and repeats this judgment if the judgment is negative.

■Transfer content recognition state: If the operation code stored in the startup register 313 is a startup request, the state machine control unit 31
1 is a stop state and an affirmative determination is made.

From the data transfer request control unit 291 to the main storage device 2
A read request for the transfer content data on the state machine control unit 311.21 is output, and the read transfer content data is sent to the state machine control unit 311.21. , MStJ address counter section 331.
The data length counter section 341 is set in the extended memory address register 317.

The state machine control unit 311 refers to the transfer content data and recognizes whether the block transfer is from the main storage device 221 to the expansion memory 231 or from the expansion memory 231 to the main storage device 221.

■Transfer start state: The state machine control unit 311 controls the expansion memory control unit 27.
5 to start the transfer processing operation, a request to start the transfer processing operation is output together with the address of the extended memory address register 317 and the data length of the data length counter section 341.

■Transfer recognition state: Next, the state machine system 71 unit 311 determines whether pro-transfer is possible or not. If the extended memory 231 is being used by another process, it makes a negative determination. , repeat this determination until it becomes usable.

■Data length confirmation state: If an affirmative determination is made in the transfer confirmation state, then the state machine control unit 311 determines that the data length of the block to be transferred is “0”.
”. This determination is made by monitoring the detection result by the data length all 0 detection unit 319, and if the determination is affirmative, there is no data to be transferred, so the process returns to the stop state.

■Main storage request generation state: If negative judgment is made in the data length confirmation state (if there is data to be transferred)
, the state machine control unit 311 generates a corresponding request based on the transfer content data referenced in the previous transfer content recognition state, and the data transfer request control unit 291
from the interface register 265. Based on the transfer data length currently held in the data length counter unit 341, when reading data from the main storage device 221, a 64-hide or 8-byte fetch request is generated and the data is stored in the main storage device 221. In this case, a 16-height or 8-hide store request is generated and output from the request generation register 321.

■Main storage device address increment state: Next, the state machine control unit 311 increases the main storage device address increment state according to the data length (number of bytes) of the sent request.
Add 1 address. State machine control unit 311
is the data length (hyde length) of the sent request in MS
[Set the addition value n of the J address 9f2 part 331,
Addition is performed by adder 337, and the addition result is stored in register 335.

(2) Data Length Subtraction State 2 Additionally, the state machine control unit 311 subtracts the held transfer data length corresponding to the data length (Hyde number) of the sent request. The state machine control unit 311 sets the data length (number of bytes) of the sent request to the subtraction value n of the data length address counter unit 341, performs subtraction using the subtracter 347, and stores the subtraction result in the register 3.
45. When this data length subtraction state ends, the process returns to the data length confirmation state and repeats the process.

■ As shown in the stop of -1, a startup request instructing a block transfer from a processor such as the central processing unit 211 is sent to the storage controller 211.
41, the data transfer request control unit 2
91 is the data length (number of bytes) that can send this block to the main storage device 221 based on the transfer content data.
Generates fetch requests or store requests corresponding to each division. In this request generation, the address of the main storage device 221 is updated by the MSUS address counter 31, and the remaining data length is calculated by the data length counter section 341. Further, the generated request is supplied to the interface register 265, and thereafter processed in the storage control device 241 in the same manner as requests supplied from the central processing unit 211 and the like, and sent to the main storage device 221.

Therefore, the bromo processor such as the central processing unit 211 does not need to generate a request for each transferred node after outputting the activation request, and the burden on the bromo processor can be reduced.

Dear JF U4, In the above-described embodiment of the present invention, the amount of data to be transferred is subtracted by the data length counter section 341 until the result of this subtraction becomes "0". Although the request generation is repeated, the request generation may be repeated by adding the amount of data that has been transferred until this amount of data becomes equal to the data amount of the entire transfer block.

In addition, a plurality of pieces of transfer content data are stored consecutively on the main storage device 221, and the data transfer request control unit 2
91 reads out these transfer contents data and devises the state shown in FIG. Data transfer becomes possible.

Furthermore, in "1. Correspondence between Examples and FIG. 1",
Although the correspondence between the present invention and the embodiments has been described, those skilled in the art will easily assume that the present invention is not limited to this and that there are various modifications.

〔Effect of the invention〕

As described above, according to the present invention, when a startup request is supplied to a storage control device, a read request or a write request with a data length that can be sent at one time based on the transfer contents is transferred in units of blocks. By repeatedly generating the data until it is completed and sending it to the main memory, the load on the processor can be reduced, which is extremely useful in practice.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the data transfer control method of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, and Fig. 3 is a detailed configuration of a data transfer request control section of an embodiment of the present invention. 4 is an explanatory diagram of request generation operation according to an embodiment of the present invention, and FIG. 5 is an overall configuration diagram of the computer system. In the figure, 111 is a processor, 113 is a main storage device, 115 is an expanded storage device, 117 is a storage control device, 121 is a means for accepting activation, 131 is a request generation means, 141 is a transfer data amount calculation means, 211 is a center Processing unit (CPU), 221 is main storage unit (MSU), 231 is extended memory, 241 is storage control unit (MCU), 251 is channel control unit (CHP), 261.263
, 265 is an interface register, 267 is a selector, 269 is a priority control unit, 271 is an access pipeline, 273 is an access source interface, 275 is an extended memory control unit, 277 is an MSU control unit, 283 is a transfer data unit, 291 is an access source interface Request control unit for data transfer, 311 is a state machine control unit, 313 is a startup register, 315 is a management information storage unit, 317 is an extended memory address register, 319 is a data length all 0 detection unit, 321 is a request generation register, 331 is a MSU address counter section 341 is a data length counter section. ``Shoshi Ito'' Nori, 71 strikes, eyeing my father's ψforce 4 to 9 zo Figure 4 All 71 moves of the calculation system 1 Kyo Hachi Figure 5

Claims (1)

[Claims] (1) It has a processor (111), a main storage device (113), an expanded storage device (115), and a storage control device (117), and the main storage device (113) and the expanded storage device (
115), in which the storage control device (117) performs data transfer in blocks;
a startup accepting means (121) for accepting a startup request supplied from the processor (111) prior to data transfer in units of blocks; Read the transfer content data on the device (113), and based on this transfer content data,
The main storage device (113) and the expansion storage device (115)
), a request generating means generates a read request or a write request in units of data length that can be transferred at one time and outputs it to the main storage device (113). (1
31), and calculates the data length of the request transferred in response to the request output from the request generating means (131), and transmitting the data to the request generating means (131) until the data length corresponds to the data length in units of blocks. a transfer data amount calculation means (141) that sends a request generation instruction;
7) A data transfer control system characterized in that a request is repeatedly sent to the main storage device (113).