JPH0368080U - - Google Patents
Info
- Publication number
- JPH0368080U JPH0368080U JP12940689U JP12940689U JPH0368080U JP H0368080 U JPH0368080 U JP H0368080U JP 12940689 U JP12940689 U JP 12940689U JP 12940689 U JP12940689 U JP 12940689U JP H0368080 U JPH0368080 U JP H0368080U
- Authority
- JP
- Japan
- Prior art keywords
- test
- terminal
- during
- logic
- turned
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims 8
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Tests Of Electronic Circuits (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Description
第１図は請求項１の考案の実施例を示す接続図
、第２図は請求項２の考案の実施例を示す接続図
、第３図は従来のＩＣ試験装置を示す接続図であ
る。
FIG. 1 is a connection diagram showing an embodiment of the invention of claim 1, FIG. 2 is a connection diagram of an embodiment of the invention of claim 2, and FIG. 3 is a connection diagram showing a conventional IC testing device.
Claims (1)
又はセンス線が接続される第１端子と、直流試験
時にセンス線又はフオース線が接続され、かつ論
理試験時にドライバ、コンパレータが接続される
第２端子と、直流試験時にガードドライバが接続
され、かつ論理試験時に接地に接続される第３端
子とが設けられ、 シールドされた同軸線の一端において、その外
導体が上記第１端子に接続されると共に論理試験
時にオンにされる第１スイツチを通じて上記第３
端子に接続され、内導体が上記第２端子に接続さ
れ、シールドが上記第３端子に接続され、 上記シールドされた同軸線の他端において、そ
の外導体が直流試験時にオンとされる第２スイツ
チを通じて被試験ＩＣ素子の１つのピンに接続さ
れると共に論理試験時にオンとされる第３スイツ
チを通じて接地に接続され、内導体が上記１つの
ピンに接続されるＩＣ試験装置。 (2) 試験装置本体に、直流試験時にフオース線
又はセンス線が接続される第１端子と、直流試験
時にセンス線又はフオース線が接続され、かつ論
理試験時にドライバ、コンパレータが接続される
第２端子と、直流試験時にガードドライバが接続
され、かつ論理試験時に接地に接続される第３端
子とが設けられ、 同軸線と単線とを共通にシールドしたケーブル
の一端において、その単線が上記第１端子に接続
され、同軸線の内導体が上記第２端子に接続され
、外導体及びシールドが上記第３端子に接続され
、 上記ケーブルの他端において、その単線が直流
試験時にオンとされる第１スイツチを通じて被試
験ＩＣ素子の１つのピンに接続され、そのピンに
内導体が接続され、外導体は論理試験時にオンと
される第２スイツチを通じて接地に接続されるＩ
Ｃ試験装置。[Scope of Claim for Utility Model Registration] (1) The test device has a first terminal to which a force line or a sense line is connected during a DC test, a first terminal to which a sense line or a force line is connected during a DC test, and a driver terminal during a logic test. , a second terminal to which a comparator is connected, and a third terminal to which a guard driver is connected during a DC test and to ground during a logic test are provided, and at one end of the shielded coaxial line, its outer conductor The third switch is connected to the first terminal and is turned on during the logic test.
a second terminal, an inner conductor is connected to the second terminal, a shield is connected to the third terminal, and at the other end of the shielded coaxial wire, the outer conductor is turned on during the DC test. An IC test device that is connected to one pin of an IC device under test through a switch, and connected to ground through a third switch that is turned on during a logic test, and whose inner conductor is connected to the one pin. (2) The test equipment has a first terminal to which a force line or sense line is connected during a DC test, and a second terminal to which a sense line or a force line is connected during a DC test and a driver and a comparator during a logic test. A terminal and a third terminal to which a guard driver is connected during a DC test and to ground during a logic test are provided. terminal, the inner conductor of the coaxial line is connected to the second terminal, the outer conductor and shield are connected to the third terminal, and at the other end of the cable, the single wire is turned on during the DC test. I is connected to one pin of the IC device under test through one switch, the inner conductor is connected to that pin, and the outer conductor is connected to ground through a second switch that is turned on during logic testing.
C test equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12940689U JPH0712940Y2 (en) | 1989-11-06 | 1989-11-06 | IC test equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12940689U JPH0712940Y2 (en) | 1989-11-06 | 1989-11-06 | IC test equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0368080U true JPH0368080U (en) | 1991-07-03 |
| JPH0712940Y2 JPH0712940Y2 (en) | 1995-03-29 |
Family
ID=31677035
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12940689U Expired - Fee Related JPH0712940Y2 (en) | 1989-11-06 | 1989-11-06 | IC test equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0712940Y2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002008775A1 (en) * | 2000-07-24 | 2002-01-31 | Advantest Corporation | Test instrument |
| JP2003512630A (en) * | 1999-10-19 | 2003-04-02 | テラダイン・インコーポレーテッド | Improved test and calibration circuit and method in automatic test equipment |
| JP2010148290A (en) * | 2008-12-19 | 2010-07-01 | Advantest Corp | Power supply apparatus and test device |
-
1989
- 1989-11-06 JP JP12940689U patent/JPH0712940Y2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003512630A (en) * | 1999-10-19 | 2003-04-02 | テラダイン・インコーポレーテッド | Improved test and calibration circuit and method in automatic test equipment |
| WO2002008775A1 (en) * | 2000-07-24 | 2002-01-31 | Advantest Corporation | Test instrument |
| JP2002040098A (en) * | 2000-07-24 | 2002-02-06 | Advantest Corp | Testing device |
| KR100733256B1 (en) * | 2000-07-24 | 2007-06-27 | 주식회사 아도반테스토 | Test equipment |
| JP2010148290A (en) * | 2008-12-19 | 2010-07-01 | Advantest Corp | Power supply apparatus and test device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0712940Y2 (en) | 1995-03-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |