JPH0368081U - - Google Patents
Info
- Publication number
- JPH0368081U JPH0368081U JP12988989U JP12988989U JPH0368081U JP H0368081 U JPH0368081 U JP H0368081U JP 12988989 U JP12988989 U JP 12988989U JP 12988989 U JP12988989 U JP 12988989U JP H0368081 U JPH0368081 U JP H0368081U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- digital
- triangular wave
- trigger
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000003786 synthesis reaction Methods 0.000 claims description 4
- 238000007689 inspection Methods 0.000 claims 1
- 230000002194 synthesizing effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
Description
第１図はこの考案の実施例を示すブロツク図、
第２図はこの考案の動作説明図、第３図は従来の
ブロツク図、第４図は従来の動作説明図である。
図においてＡ……入力印加電圧、Ｂ……＋スロ
ープスレツシヨルドレベル、Ｃ……−スロープス
レツシヨルドレベル、Ｄ……デイジタルＩＣ出力
、Ｅ……ハイレベルコンパレータ出力、Ｆ……ロ
ーレベルコンパレータ出力、Ｇ……トリガ合成回
路出力、Ｈ……波形モニタ表示波形、１……直流
標準電圧発生器、２……デイジタルＩＣ、３……
レベル判定回路、４……三角波発生回路、５……
ハイレベルコンパレータ、６……ローレベルコン
パレータ、７……トリガ合成回路、８……波形モ
ニタ回路である。なお図中、同一符号は同一又は
相当の部分を示す。
Figure 1 is a block diagram showing an embodiment of this invention.
FIG. 2 is an explanatory diagram of the operation of this invention, FIG. 3 is a conventional block diagram, and FIG. 4 is an explanatory diagram of the conventional operation. In the figure, A...Input applied voltage, B...+Slope threshold level, C...-Slope threshold level, D...Digital IC output, E...High level comparator output, F...Low level comparator Output, G...Trigger synthesis circuit output, H...Waveform monitor display waveform, 1...DC standard voltage generator, 2...Digital IC, 3...
Level judgment circuit, 4... Triangular wave generation circuit, 5...
High level comparator, 6...low level comparator, 7...trigger synthesis circuit, 8... waveform monitor circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.
Claims (1)
ヨルドレベルをカバーしたレベルの三角波を発生
する三角波発生回路と、被試験デイジタルＩＣの
出力信号のローレベル、ハイレベルを検出し、ト
リガ信号を出力する。 ローレベルコンパレータおよびハイレベルコン
パレータと、前記各トリガ信号を合成するトリガ
合成回路と、前記三角波発生回路出力をトリガ合
成回路出力で輝度変調をかけて表示する校正され
た垂直軸を持つ波形モニタ回路とを備えたデイジ
タルＩＣ検査装置。[Scope of Claim for Utility Model Registration] A triangular wave generation circuit that generates a triangular wave with a level that covers each slope threshold level at the input end of a digital IC, and a circuit that detects the low level and high level of the output signal of the digital IC under test. , outputs a trigger signal. a low level comparator and a high level comparator, a trigger synthesis circuit for synthesizing the respective trigger signals, and a waveform monitor circuit having a calibrated vertical axis for displaying the output of the triangular wave generation circuit by subjecting it to brightness modulation using the output of the trigger synthesis circuit. Digital IC inspection equipment equipped with
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12988989U JPH0368081U (en) | 1989-11-07 | 1989-11-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12988989U JPH0368081U (en) | 1989-11-07 | 1989-11-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0368081U true JPH0368081U (en) | 1991-07-03 |
Family
ID=31677488
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12988989U Pending JPH0368081U (en) | 1989-11-07 | 1989-11-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0368081U (en) |
-
1989
- 1989-11-07 JP JP12988989U patent/JPH0368081U/ja active Pending
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