JPH036834A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To reduce extra surface leak current without changing characteristics of an FET by forming a gate electrode in a recess of a first stage and by forming a layer of low concentration having a carrier concentration of 1X10<17>cm<-3> or below at a thickness of 1000Angstrom to an exposed surface excepting the recess whereon the gate electrode is formed. CONSTITUTION:A carrier concentration of a low concentration layer 6a which is formed on a surface of an active layer 2 having a thickness of 1000Angstrom and a carrier concentration of 1X10<17>cm<-3> or below may be either of being undoped or of a polarity which is reverse to the active layer 2. Since the surface of the active layer 2 is covered with the low concentration layer 6a, or it is of a low concentration or undoped the numbers of carriers is small compared with a conventional one. Therefor, even if a passivation film is formed thereon and interface conditions with the low concentration layer 6a vary a little, a leak current is not generated easily in the interface because few carrier exists in the low concentration layer 6a in itself. According to this constitution, it is possible to restrain a gate reverse leak current stably.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor (hereinafter abbreviated as FET) in which gate reverse leakage current is reduced.

[Prior Art] FIG. 5 is a cross-sectional structural diagram of a conventional FET. In this figure, 1 is a semi-insulating semiconductor substrate, and this semiconductor substrate 1
An active layer 2 is provided thereon, and on this are source and drain electrodes 3.4 of ohmic contact and a gate electrode 5 of Schottky junction.
is formed to constitute an FET. In the gate area,
The active layer 2 has a recessed structure with grooves.

In an FET having such a structure, since the surface of the active layer 2 (the shaded area in FIG. 5) is exposed, there is a drawback that the characteristics of the FET change over time due to changes in the surface condition. For this reason, in normal FETs, the surface is stabilized,
In order to stabilize the FET characteristics, a telephone body film made of SiN or 5i02, called a passivation film 8, is formed on the surface, as shown in FIG.

[Problem to be solved by the invention]

However, when the passivation film 8 and the active layer 2 are made of Si, a reproducible and stable interface can be obtained with 5iO7, but when GaAs is used as the material, a reproducible and stable interface can be obtained with either material. difficult to obtain. Therefore, the state of the interface changes depending on the conditions for forming the passivation film 8, and the characteristics of the FET also change. In particular, this change in the characteristics of the FET is expressed in the reverse leakage current of the gate (hereinafter abbreviated as ■). ■, acts as a noise source in a small signal low noise FET, so it is preferable to make it as small as possible.
Regarding T, it is better to have a smaller number from the viewpoint of reliability and efficiency when operating with a large amplitude.

However, in the conventional structure, there was a large change in the value of (■) due to the instability of the interface, which caused problems not only in terms of high performance but also in terms of reproducibility and reliability.

As mentioned above, in the conventional FET, the FET characteristics change due to changes in the interface state depending on the formation conditions of the passivation film 8.
In particular, fluctuations in gate reverse leakage current occur, which poses a problem in improving the performance and reliability of FETs.

This invention was made to solve the above-mentioned problems, and regardless of the formation conditions of the passivation film,
The object of the present invention is to obtain a field effect transistor that can always keep stable gate reverse leakage current to a low level.

[Means to solve the problem]

The field effect transistor according to claim (1) of the present invention includes a source electrode and a drain electrode in ohmic contact on an active layer having a desired thickness formed on a semiconductor substrate, and has one stage on the active layer. Alternatively, a plurality of recesses are formed, a gate electrode is formed in the first recess, and a thickness of 100 mm is formed on the surface of the exposed part other than the recess where the gate electrode is formed.
Below 0 Å, the carrier concentration is 1 x 1017 cm −
'The following low concentration layer is formed.

Further, in the invention described in claim (2), the low concentration layer is formed of a semiconductor having a larger band gap than the active layer and which can have good lattice matching with the active layer.

Further, in the field effect transistor according to claim (3) of the present invention, the carrier concentration on the active layer having a desired thickness formed on the semiconductor substrate is I x 10"cm.
Form a first low concentration layer with a thickness of -3 or less and a thickness of 1000A or less, on which the carrier 4 degree is 3xlO17cm-3
Forming the above high concentration layer, further forming a second low concentration layer under the same conditions as the first low concentration layer, and forming a recess bottom below the interface between the first low concentration layer and the active layer. A first stage recess is formed so that the recess surface is covered with the first low concentration layer, a surface of the high concentration layer is covered with the second low concentration layer, and the surface of the second stage recess is covered with the second low concentration layer. The source electrode and drain electrode are formed by ohmic contact.

[Effect]

In the invention described in claims (1) and (2) of the present invention, since a low concentration layer is formed on the surface of the exposed part other than the recess where the gate electrode is formed, the surface carrier concentration is lower than before. The reverse leakage current of the FET can be reduced regardless of the conditions for forming the passivation film.

Further, in the invention described in claim (3) of the present invention, the bottom surface of the recess in which the gate electrode is formed is located below the interface between the active layer and the first low concentration layer, and the bottom surface of the recess in which the gate electrode is formed is located below the interface between the active layer and the first low concentration layer. A part of the first low concentration layer covers the second layer surface, and a part of the first low concentration layer covers the surface of the high concentration layer formed on the first low concentration layer.
Since it is covered with a low concentration layer, it has the characteristics of low source parasitic resistance, high breakdown voltage, and low leakage current.

〔Example〕

(Example 1) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view of a field effect transistor showing an embodiment of the present invention. In this figure, 1 to 5 are the same as in FIG. 5, and 6a is a layer formed on the surface of the active layer 2 with a thickness of 1000 Å or less and a carrier concentration of I x 10"cm.
It is a low concentration layer below -'. The carrier concentration of this low concentration layer 6a may be non-doped or may have a polarity opposite to that of the active layer 2. In addition, in the structure shown in FIG. 1, it is better to make the source/drain electrodes 3 and 4 in ohmic contact contact with at least the active layer 2 below which the low concentration layer 6a is etched off, from the point of view of reducing the ohmic contact resistance. preferable. In the case of the structure shown in FIG. 1, the surface of the active layer 112 is covered with the low concentration layer 6a, or is lightly doped or non-doped, so there are fewer carriers than in the past.

Therefore, even if a passivation film is formed on this layer and the state of the interface with the low concentration layer 6a changes somewhat, leakage current is unlikely to occur at the interface since there are originally few carriers in the low concentration layer 6a. Therefore, with such a structure, the gate reverse leakage current can be stably suppressed. Moreover, since the structure directly under the source/drain electrodes 3 and 4 and the gate electrode i5 can inherit the conventional structure, only the excess surface leakage current can be reduced without changing the characteristics of the FET itself.

(Embodiment 2) FIG. 2 is a sectional view of a field effect transistor showing another embodiment of the present invention. The FET with the structure shown in FIG. 2 is designed to improve the breakdown voltage without significantly deteriorating the source parasitic resistance of the FET with the structure shown in FIG.
Fig. 2 shows the case of a two-stage recess, and this also applies to the case of 63 stages or more. Second
In the embodiment shown in the figure, the surface of the second stage recess newly generated from the embodiment shown in FIG. 1 is similarly covered with a low concentration layer 6b.

As for the manufacturing method to obtain the structure shown in FIG. 2, first, a low concentration layer 6a is formed on the active layer 2, and after forming a recess with a wider opening width (second stage), as shown in the figure. Then, a low concentration layer 6b is epitaxially grown on the recess surface, or
Alternatively, after formation using ion implantation, a first stage recess in which the gate electrode is formed is formed, and the gate electrode 5 is formed on the bottom surface of the recess from which the low concentration layer 6b has been removed. With such a structure, it is possible to realize an FET that has the low source resistance and high withstand voltage characteristic of multi-stage recesses, and also has the characteristic of low leakage current shown in the embodiment of FIG.

(Example 3) By the way, in order to obtain the structure of the example shown in FIG. 2, it is necessary to perform epitaxial growth, ion implantation, etc. after forming the second stage recess, which makes manufacturing difficult. An embodiment for solving this manufacturing difficulty will be described with reference to FIG.

FIG. 3 shows an embodiment of the second aspect of the present invention, in which the carrier concentration is 1× on the active layer 2 having a desired thickness.
The first layer is 1017 cm-3 or less and has a thickness of 1000 Å or less.
A low concentration Fi6a with a carrier concentration of 3 is formed on top of the low concentration Fi6a.
Using an epitaxial wafer having a structure in which a high concentration layer 7 with a thickness of 1017 cm-" or more is provided, and a second low concentration layer 6b which is the same as the conditions shown in FIG. A two-stage recess FET is formed using the manufacturing method used to obtain a two-stage recess in a conventional structure without 6a and 6b.The active layer 2 and the first low concentration layer 6
The interface a is located above the bottom surface of the first stage recess, and its thickness is preferably 1000 Å or less at most in terms of characteristics. In this case, the effect of the two-stage recess is the same as in the case of FIG. Also, 1st. The surface leakage current reduction effect of the second low concentration layers 6a and 6b is also similar to that shown in FIG. However, the first low concentration layer 6a, a layer with few carriers, is different from that in FIG.
Since it is also located in a region other than the recess, that is, under the high concentration layer 7, there is a risk that the parasitic resistances R, , R, of the gate-source and gate-drain may increase in this region. However, in the structure of FIG. 3, the first low concentration layer 6 in that part
Since the high concentration layer 7 compensates for the decrease in carriers due to a, there is no risk of an increase in the parasitic resistance R8°Rd. Therefore, the structure shown in FIG. 3 has the characteristics of low source parasitic resistance and high withstand voltage due to the two-stage recess, and furthermore, low leakage current can be realized with ease of manufacture.

(Example 4) In the above Examples 1 to 3, the low concentration layers 6a and 6b are the active layer 2.
Therefore, the active layer 2 and the low concentration N6a were considered to be homojunctions. This embodiment is the low concentration layer 6a.

6b is made of a semiconductor that has a larger band gap (lower electron affinity) than the active layer 2 and has good lattice matching with the active layer 2 (for example, if the active layer 2 is GaAs, the low concentration layers 6a and 6b are made of a material such as AlGaAs). Consider the case where FIG. 4 shows the surface of the low concentration layer 6a and the energy band diagram between the low concentration layer 6a and the active layer 2 at this time. At this time, the electrons in the low concentration layer 6a migrate toward the active layer 2, which has a large electron affinity, so by optimizing the thickness and carrier concentration of the low concentration layer 6a, the low concentration layer 6a is completely depleted. (to a state without a carrier), it is possible to
Leakage current at the surface of the low concentration layer 6a can also be drastically reduced. In addition, when the active layer 2 is made of GaAs, AlGaA
The low concentration layer 6 is made of a material that essentially has fewer surface states than the material of the active layer 2, such as the combination of the low concentration layers 5a and 5b of s.
It is possible to choose between a and 6b. By using such a material for the low concentration layers 6a and 6b in FIGS. 1 to 3, excess surface leakage current can be further reduced without changing the characteristics of the FET.

(Effects of the Invention) As explained above, the invention described in claim (1) of the present invention provides an ohmic contact source electrode and a drain electrode formed on an active layer having a desired thickness formed on a semiconductor substrate. , one or more stages of recesses are formed in the active layer, a gate electrode is formed in the N1-stage recess, and a thickness of 100 mm is formed on the surface of the exposed part other than the recess where the gate electrode is formed.
Below 0 Å, the carrier concentration is I x 10”cm −’
The following low concentration layer is formed, and the claim
As described in (2), by forming a low concentration layer made of a semiconductor that has a larger bandgap than the active layer and has good lattice matching with the active layer, excess surface leakage current can be reduced without changing the characteristics of the FET. This has the effect of reducing

Further, the invention according to claim (3) of the present invention provides an active layer having a desired thickness formed on a semiconductor substrate with a carrier concentration of ix t O"cm-' or less and a thickness of 1
A first low-concentration layer with a thickness of 000 Å or less is formed, a high-concentration layer with a carrier concentration of 3×1017 cm-' or more is formed thereon, and a second low-concentration layer under the same conditions as the first low-concentration layer is formed thereon.
A first recess is formed so that the bottom of the recess is below the interface between the first low concentration layer and the active layer, and the surface of the second recess is connected to the first low concentration layer. The surface of the high concentration layer is covered with a second low concentration layer, and the source and drain electrodes are formed on the active layer by ohmic contact, making it easier to achieve low parasitic resistance, high breakdown voltage, and low leakage. It has the effect of achieving current.

[Brief explanation of drawings]

FIG. 1 and FIG. 2 each show an embodiment of the present invention.
A cross-sectional view of ET, FIG. 3 shows another embodiment of the present invention.
A cross-sectional view of the ET, FIG. 4 is a diagram showing the energy bands of the active layer and low concentration layer of the present invention, and FIGS. 5 and 6 are diagrams of the conventional F
A cross-sectional view of ET is shown. In the figure, 1 is a semiconductor substrate, 2 is an active layer, 3.4.5
are source, drain, and gate electrodes, 5a and 5b are low concentration layers, and 7 is a high concentration layer. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (3)

[Claims] (1) A source electrode and a drain electrode in ohmic contact are provided on an active layer formed on a semiconductor substrate, one or more recesses are formed in the active layer, and a gate electrode is provided in the first recess. and a low concentration layer having a thickness of 1000 Å or less and a carrier concentration of 1×10^1^7 cm^-^3 or less is formed on the surface of the exposed part other than the recess where the gate electrode is formed. Field effect transistor. (2) The low concentration layer has a larger band gap than the active layer,
2. The field effect transistor according to claim 1, wherein the field effect transistor is made of a semiconductor that can achieve good lattice matching with the active layer. (3) A layer with a carrier concentration of 1×10^1^7 cm^-^3 or less and a thickness of 10 cm on the active layer formed on the semiconductor substrate.
A first low concentration layer having a thickness of 00 Å or less is formed, a high concentration layer having a carrier concentration of 3×10^1^7 cm^-^3 or more is formed thereon, and the first low concentration layer is further formed thereon. A second low concentration layer is formed under the same conditions as above, a first stage recess is formed so that the bottom of the recess is below the interface between the first low concentration layer and the active layer, and a second stage recess is formed under the same conditions as the first low concentration layer and the active layer. The recessed surface of the first
a second low concentration layer covering the surface of the high concentration layer, and a source electrode and a drain electrode formed on the high concentration layer by ohmic contact.