JPH0368878A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To ship an LSI device ensured in its high frequency characteristics by comparing the data outputted from a logical circuit with the expected value data corresponding to test data in an external testing means to perform a test. CONSTITUTION:In this semiconductor integrated circuit device, for example, a circuit 10 oscillating a high frequency clock and a circuit 20 selecting the high frequency clock are used in a chip. The clock CLKS wherein two kinds of the through-mode clock and two-pulse mode clock selected and outputted from the clock selecting circuit 20 is used to reject the abnormality of the delay (a part shown by hatching) of the Q-output of a flip-flop 34. In this case, though the use frequency of an LSI tester is as low as 60MHz, the inferiority of high frequency of 600MHz can be partially rejected.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a technique for testing a semiconductor integrated circuit device, particularly a large-scale integrated circuit (LS1) having multiple bins and high frequency performance, by supplying a clock from the outside. Even if the frequency of the test clock is relatively low, it enables dynamic function tests that correspond to the high-frequency actual operation of internal circuits, reducing production costs while guaranteeing high-frequency characteristics with high reliability. For the purpose of a selection circuit that selects one of the clock signals in response to a control signal from the external test means and outputs the selection or lock signal at predetermined time intervals; and a clock signal selected and output by the selection circuit. and a logic circuit that executes a predetermined operation in response to test data from the external test means, and the data output from the logic circuit is input to the external test means as expected value data corresponding to the test data. A test is performed by comparison, and the test is performed in combination multiple times on different clock signals selected and output by the selection circuit.

[Industrial application field]

The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique for testing a large-scale integrated circuit (LS1) with a large number of pins and high frequency performance by supplying a clock from the outside.

[Prior art and problems to be solved by the invention]

In recent years, in the LSI field, in response to the demand for high system integration and high speed (high system clock), the LSI itself has already been developed with several hundred signal bins and a system clock of 300M.
■, SI with a frequency of about Hz to 600 MHz has been commercialized. On the other hand, when a manufacturer tests this LSI before shipment, the LSI tester uses an LSI tester, the number of pins of which increases with LSI, but the frequency of the test clock signal is 100M at most.
Since the frequency range is about Hz to 200 MHz, it is currently impossible to test at the frequency at which LSIs are actually used.

In the conventional technology, after the LSI is mounted, a test is conducted to determine whether it operates at high frequencies, and if the LSI does not operate due to mounting, the relationship with other LSIs and ICs on the printed board becomes complicated. Not only is it difficult to identify a defective LSI, but it is also difficult to remove a multi-pin LSI from a printed circuit board once it has been mounted, resulting in a large amount of waste.

In addition, since LSI testers often use LSI as a component, in order to make the LSI tester faster, it is necessary to use small-scale integrated circuits (SS), which are even faster than the LSI.
1) etc., it is necessary to make an LSI tester, which increases both cost and production time.

The present invention was created in view of the problems in the prior art, and enables dynamic function testing that corresponds to the high-frequency actual operation of internal circuits even when the frequency of the external test clock is relatively low. It is an object of the present invention to provide a semiconductor integrated circuit device that can guarantee high frequency characteristics with high reliability while reducing production costs.

[Means to solve the problem]

As shown in the principle block diagram of FIG. 1, the semiconductor integrated circuit device according to the present invention oscillates a clock signal CK2 having a higher frequency than the frequency of the clock signal CKI from the external test means 4 in synchronization with the clock signal CKI. circuit 1, selecting either a portion of the oscillated high-frequency clock signal or a clock signal from the external test means in response to a control signal C from the external test means, and applying the selected clock signal to a predetermined value. Time interval t. a logic circuit 3 that executes a predetermined operation in response to a clock signal CK3 selected and output by the selection circuit and test data TO from the external test means; A test is performed by comparing the data D output from the logic circuit with the expected value data T8 corresponding to the test data in the external test means, and the test is performed on a different clock signal selected and output by the selection circuit. It is characterized in that it is executed in combination multiple times.

E-action] FIG. 2 shows the concept of the test method for the apparatus shown in FIG. 1, and in the illustrated example, a predetermined time interval t. 1 selected and output for each
The operation timing when performing a high frequency test of a logic circuit using pulse mode and two-pulse mode clocks is shown.

In FIG. 2, (a) shows the original waveform during actual high-frequency operation, and (b) and (C) show waveforms that partially have the same frequency as the waveform in (a). As shown in the figure, the clock signal CK3 output from the selection circuit 2 is a low frequency clock signal C supplied from the external test means 4.
Since it is synchronized with KI, the external test means 4 can judge the output of the logic circuit 3.

In the case of FIG. 2(b), two pulses form a set at every predetermined time interval t0 to form a partial high frequency wave. When the leading edges (rising edges) of the clock pulse in Fig. 2(a) are numbered L2.3, . . ., respectively, 1, 2.3, and 4 in Fig. 2(b).
．． The time intervals between 5 and 6 are the same as the time intervals (■, ■, ■) between 1 and 2.3, 4.5 and 6 in FIG.

In the case of FIG. 2(C), the first time interval t. A partial high-frequency wave of one pulse is formed at the time interval, and from the next time interval onward, a set of two pulses is formed to form a partial high-frequency wave. The first pulse formed here may be a 1 (indicated by a solid line) in the low frequency clock signal C from the external test means 4 or a portion of the high frequency clock signal CK2 (indicated by a dashed line). In this case, each time interval between 2 and 3.4 and 5 is as shown in the figure (a).
The time intervals between 2 and 3.4 and 5 are the same as ■ and ■.

Therefore, the data D output from the logic circuit 3 in response to the partial high-frequency clock signal CK3 shown in FIG. 2(b) matches the expected value data TE, and the partial high-frequency clock signal CK3 shown in FIG. When the data D output from the logic circuit 3 in response to the high-frequency clock signal CK3 matches the expected value data TE, the operation corresponding to the waveform during high-frequency actual operation shown in FIG. Become.

According to the configuration of the present invention, only the inside of the chip is partially operated at a high frequency in synchronization with the (low frequency) clock input from the external test means 4, and the output of the chip is tested at a low frequency. , such tests are combined and executed multiple times for different clock signals CK3 selected and output by the selection circuit 2.

Note that other structural features and details of the operation of the present invention will be explained using the embodiments described below with reference to the accompanying drawings.

〔Example〕

FIG. 3 shows the configuration of a semiconductor integrated circuit device as an embodiment of the present invention.

In the figure, LSI refers to a semiconductor integrated circuit in the form of a chip (
LS1) The device is roughly divided into clock oscillation circuit IO
, a clock selection circuit 20 , and a logic circuit 30 . LSIT stands for LSI tester, LS
Test data OAT for each circuit in the I device LSI
and active low low frequency clock signal CLK
(60 MHz in this embodiment), the selection control signal SF! to the driver 41, the clock oscillation circuit 10, and the clock selection circuit 20. L1. The driver 42 that supplies S[1iL2 and the output data 1 from the logic circuit 30
) out with expected value data BXD corresponding to test data DAT.

The clock oscillation circuit 10 includes an inverter 11 that responds to a low frequency clock signal CLK from an LSI tester, and two sets of ring oscillation circuits 12.1 that respond to the output of the inverter.
3 and the high frequency output clock signal C of the ring oscillation circuit.
The selection control signal 5 from the driver 42 selects either the LKII or the low frequency clock signal CLK from the LSI tester.
The multiplexer 14 selects in response to the BLI. One of the two ring oscillation circuits 12 consists of one directly connected NOR gate and 2m inverters, and the other ring oscillation circuit 13 consists of one directly connected NOR gate and 2n inverters. ing.

In other words, the output frequency of each ring oscillation circuit is (2
The frequency is increased to m+1) and (2n+1) steps. The clock signal selected by the multiplexer 14 is assumed to be CLKI.

The clock selection circuit 20 receives the output clock signal CLKI of the multiplexer 14 and the voltage signal V at a predetermined potential.

a D-type flip-flop (FF) 21 responsive to the output signal of the flip-flop and an output clock signal CLKI of the multiplexer 14; It consists of an OR gate 23 that responds to the signal CLKI, and a multiplexer 24 that selects either the output signal of the OR gate 23 or the low frequency clock signal CLK from the LSI tester in response to the selection control signal 5EL2 from the driver 42. There is. Note that low frequency clock signals CL and K from the LSI tester are applied to the reset terminals R3T of the D-type flip-flops 21 and 22 via the inverter 25.

Further, the clock signal selected by the multiplexer 24 is assumed to be ('LKS).

The logic circuit 30 is used as a circuit under test, and includes an AND gate 31 that responds to a low frequency clock signal CLK and a test mode signal from an LSI tester, and an output of the AND gate and outputs CLKS and LS of the multiplexer 24.
A shift register responsive to the test data OAT from the driver 41 in the I tester, and a shift register responsive to the output of the shift register to output the output data D06. Buffer 3 that generates
It consists of 6. The shift register consists of four D-type flip-flops 32 to 35 that are directly connected.
The output CLKS from the multiplexer 24 is applied to the clock terminal CK of each flip-flop, and the output of the AND gate 31 is applied only to the clock terminal CK of the flip-flop 32.

FIG. 4 shows an example of the waveform of the input/output signal of the clock oscillation circuit 10, and FIG. 5 shows an example of the waveform of the input/output signal of the clock selection circuit 20.

In the example shown in Figure 4, three types of clocks are generated in synchronization with the low frequency clock CLK from the LSI tester, namely, the low frequency clock through output CLK, and the high frequency clock output CL corresponding to the (2m+1) stage ring oscillation circuit. Hl and a high frequency clock output CLKH corresponding to the (2n+1) stage ring oscillation circuit are generated.

In the example shown in FIG. 5, three types of clocks are generated in synchronization with the high frequency clock CLKI (600 MHz in this embodiment) from the clock oscillation circuit 10, that is, low frequency (60 MHz in this embodiment) through output CLK, 600 MHz.
z high frequency clock output CLKI and partially 6
A clock output with a high frequency of 00 MHz and low frequencies in other parts is generated. In this case, the desired frequency can be obtained by changing the number of stages of the ring oscillation circuit described above.

FIG. 6 shows an example of a signal waveform in the high-speed actual operation mode of the shift register in FIG. 3.

The illustrated example has a frequency of 600 MHz (period 1.67 ns
), the flip-flop 34 causes a malfunction (the part indicated by hatching), and its Q output is transmitted to the next-stage flip-flop 35 with a delay of more than a predetermined time (tpd). In this case, the delay (t pd' ) of the Q output of the flip-prop 34 is a defect that is rejected only during high frequency operation.

If the delay time of the Q output during normal operation of the flip-flop 34 is tp(1, the delay time of the Q output during abnormal operation is tpd', and the setup time of the flip-flop 35 in the next stage is ts, then the following equation is given. holds true.

tpd+ts≦1.57ns ・・・・・・During normal operation tpd+ts >1.67ns −・−−−−During defective operation From these equations, when the test period is large, that is, when the test clock (supplied from the LSI tester) It can be seen that when the clock frequency is low, defects cannot be rejected.

To deal with this, in this embodiment (FIG. 3), a circuit (0) for oscillating a high frequency clock and a circuit 20 for selecting the high frequency clock are used in the chip.

FIG. 7 shows an example of a signal waveform when testing the device shown in FIG. 3.

In the example shown in FIG. 7, the clock CLKS, which is a combination of two types of clocks, the through mode clock and the two-pulse mode clock, selected and output by the clock selection circuit 20 is used to delay the Q output of the flip-flop 34 (hatching). The waveform when rejecting the abnormality in the part shown by is shown.

As shown in the figure, the operating frequency of the LSI tester is 60M
Although the frequency is as low as 60 Hz,
It is possible to reject defects in high frequency actual operation at 0 MHz.

In the above-described embodiment, the clock oscillation circuit 10 and the clock selection circuit 20 were configured separately, but this is different from the clock generation circuit in which both circuits are configured as one circuit, as shown in FIG. 8(a), for example. The circuit 50 may also be used.

The clock generation circuit 50 illustrated in FIG. 8(a) is
As shown in Figure (b), the low frequency clock C
an inverter 51 that responds to the output of the inverter and the low frequency clock input CL; an inverter 53 that responds to the low frequency clock input CL; and an inverter 53 that responds to the output of the inverter 53. 54; an inverter 55 responsive to the output of the inverter 54; an AND gate 56 responsive to the outputs of the inverters 54 and 55; an OR gate 57 responsive to the outputs of the AND gates 52 and 56; A multiplexer 58 that selects one of the frequency clocks CLK in response to the selection control signal SEL.
It is composed of.

FIG. 9 shows an example of signal waveforms at various parts in the circuit of FIG. 8.

As shown in the figure, in the circuit configuration of Figure 8, the chopper (51, 52) generates a one-pulse partial high-frequency signal in response to the low-frequency clock CLK from the LSI tester, and One chopper <53-56>
This generates one pulse of a partial high frequency signal, creating a total of two pulses of partial high frequency signals.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to ship an LSI device with guaranteed high frequency characteristics even though a low frequency external test means is used, thereby improving reliability.

Moreover, defects in high frequency characteristics due to mounting can be rejected at the time of shipment of the LSI device.

Furthermore, since highly reliable testing is possible even by using low-cost external testing means, it is possible to reduce the production cost of the LSI device and, by extension, the mass production cost of the entire system.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of a semiconductor integrated circuit device according to the present invention, FIGS. 2(a) to (C) are operation timing diagrams for explaining the concept of the test method for the device shown in FIG. 1, and FIG. 4 is a waveform diagram showing an example of input/output signals of the clock oscillation circuit in FIG. 3; FIG. 5 is a circuit diagram showing an example of input/output signals of the clock selection circuit in FIG. 3; FIG. A waveform diagram showing an example; FIG. 6 is a diagram showing an example of the signal waveform in the high-speed actual operation mode of the shift register in FIG. 3; FIG. 7 is a signal waveform diagram for explaining the test method for the device in FIG. 3. , FIGS. 8(a) and 8(b) are circuit diagrams showing the configuration of main parts in another embodiment of the present invention, and FIG. 9 is a signal waveform diagram of each part in the circuit of FIG. 8. (Explanation of symbols) 1... Clock signal oscillation circuit, 2... Clock signal selection circuit, 3... Logic circuit, 4... External test means, 1. CK2. CK3...Clock signal, C.
...Control signal, TO...Test data 1 D...(Logic circuit) output data, TE...Expected value data.

Claims (1)

[Claims] A circuit (1) that oscillates a clock signal (CK2) having a higher frequency than the frequency of the clock signal in synchronization with a clock signal (CK1) from an external test means (4); Selecting either a portion of a high frequency clock signal or a clock signal from the external test means in response to a control signal (C) from the external test means, and transmitting the selected clock signal at predetermined time intervals (t_0). a selection circuit (2) that outputs an output to ), a test is performed by comparing the data (D) output from the logic circuit with expected value data (TE) corresponding to the test data in the external test means, and the test is performed by comparing the data (D) output from the logic circuit with the expected value data (TE) corresponding to the test data. 1. A semiconductor integrated circuit device characterized in that a combination of different clock signals selected and output by a plurality of clock signals is executed multiple times.