JPH0370229A - Data comparison synchronizing system serial communication system - Google Patents

Abstract

PURPOSE:To confirm a fault of a communication line or receiving operation at a receiver side by sending back a received data to a reception line not required at the sender side via a transmission line not required at the receiver side synchronously with a clock signal, and allowing the sender side to compare the transmission data and the reception data. CONSTITUTION:Shift registers 1, 1' send a parallel data 2 from a transmission line 6 at the time of transmitting and receives a serial data from a reception line 11 at the time of receiving, and outputs the data as a parallel data 12. The sender side transmission line 6 and the receiver side reception line 11, the receiver side transmission line 10 and the sender side reception line 7, and a sender side clock line 8 and a receiver side clock line 9 are coupled by a communication line 13. Then the transmission data is inputted to a comparator 5, and simultaneously inputted to the other input of the comparator via the sender side transmission line 6, the receiver side reception line 11, the receiver side transmission line 10 and the sender side reception line 7 and outputted as a comparison output 3. Thus, the communication data is checked at the same time of transmission.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock synchronous half-duplex serial communication system.

[Summary of the invention]

In a clock-synchronized half-duplex serial communication system, the present invention transmits received data back in synchronization with a clock signal to an unnecessary receiving line on the transmitting side via an unnecessary transmitting line on the receiving side. By comparing the signals, it is possible to check for abnormalities in the communication line or the receiving operation on the receiving side.

[Conventional technology]

Conventionally, communication data has been checked using a method of adding parity focus or a method of returning data sent by software and comparing the data.

[Problem to be solved by the invention]

However, the conventional clock-synchronized half-duplex serial communication system has disadvantages in that the parity bit check requires a heavy burden on hardware and software, and the communication speed is sacrificed due to the communication data check.

SUMMARY OF THE INVENTION In order to solve these conventional drawbacks, the present invention aims to check communication data simultaneously with transmission using a small amount of hardware.

[Means to solve the problem]

In order to solve the above problems, this invention sends back the data sent to the receiving side via an unnecessary receiving line at the time of transmission, and the sending side compares the transmitted data and the returned data using a comparator. By doing this, the communication data is checked at the same time as sending.

[Effect]

The data shifted by the clock line is sent out from the transmission line on the sending side, and is received by the receiving side on the receiving side. The received data is received by the shift register on the receiving side, while being sent back as is from the transmission line on the receiving side. The communication line is checked by comparing transmitted data and received data using a comparator on the transmitting side.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

In FIG. 1, the shift register 1.1' sends out parallel data 2 from the transmission line 6 during transmission, and inputs serial data from the reception line U and outputs it from the parallel data 12 during reception. A transmitting side transmission line 6 and a receiving side receiving line 11. The receiving side transmission line 10 and the sending side receiving line 7 and the sending side clock line 8 and the receiving side clock line 9 are coupled by a communication line 13. The transmission data is input to the comparator 5, and at the same time, it is input to other inputs of the comparator 5 via the transmission line 6 on the transmission side, the reception line 11 on the reception side, the transmission line 10 on the reception side, and the reception line 7 on the transmission side, and is compared. and output as comparison output 3. The clock signal has a frequency equal to the baud rate, and is input to the shift registers 1 and 1' at the same time as being input to inform the comparison timing of the comparator 5.

In FIG. 2, one bit is added to the shift register. Here, shift registers 1 and 1' send parallel data 2 (sent from 816) during transmission, and input serial data from reception vAll during reception, and input parallel data 1 from reception vAll.
Output from 2. Sending side sending vA6 and receiving side receiving vAl
1. The receiving side transmission vAlo and the sending side receiving line 7 and the sending side clock line 8 and the receiving side clock line 9 are coupled by a communication line 13. The transmission data is shifted by 1 pin by the 1-bit shift register after the shift register 1 and inputted to the comparator 5, and at the same time, the data before entering the 1-bit shift register is transferred to the transmission line 6 on the transmitting side and the data on the receiving side. The data is shifted by 1 bit by the shift register 1' via the reception line 11, and is input to the other input of the comparator 5 via the reception side transmission vAlo and the transmission side reception line 7, and is compared, and the comparison output 3 is output as

The clock signal has a frequency equal to the baud rate, and is input to the shift register 1.1' at the same time as being input to inform the comparison timing of the comparator 5.

〔Effect of the invention〕

As explained above, this invention can check communication data with a small amount of hardware, and can increase the amount of communication data even if the same baud rate as the conventional one is used, thereby improving the quality of communication data. It has the effect of

Furthermore, it is also possible to match it with conventional communication methods by ignoring the comparison output.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the invention. FIG. 2 is a block diagram of the above invention in which 1 bit of shift register is added. Shift register (transmission) Shift register (reception) Parallel transmission data comparison output Clock signal comparator Transmission side transmission line Transmission side reception line Transmission side clock line Receiving side cross line, Receiving side transmission line, Receiving side receiving line, Parallel receiving data communication line

Claims (2)

[Claims] (1) In synchronous serial communication, which consists of a shift register and a comparator, and has a transmitting line, a receiving line, and a clock line, transmitting data is sent back from the receiving side in synchronization with the clock, and the transmitting side compares this data with the transmitted data. A synchronous serial communication method that is characterized by being able to detect whether the communication line is normal. (2) Synchronous serial communication according to claim 1, characterized in that by adding a shift register of one or more bits to the above method, it is possible to detect from the transmitting side that the receiving side has successfully taken in data into the shift register. method.