JPH0370476U - - Google Patents
Info
- Publication number
- JPH0370476U JPH0370476U JP13245289U JP13245289U JPH0370476U JP H0370476 U JPH0370476 U JP H0370476U JP 13245289 U JP13245289 U JP 13245289U JP 13245289 U JP13245289 U JP 13245289U JP H0370476 U JPH0370476 U JP H0370476U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- video signal
- horizontal synchronization
- input terminal
- synchronization signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Television Signal Processing For Recording (AREA)
Description
第１図は本考案の一実施例を示す図、第２図は
従来例を示す図である。
２４……遅延回路。
FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional example. 24...Delay circuit.
Claims (1)
号より水平同期信号を分離する水平同期信号分離
回路１２と、 この水平同期信号分離回路１２からの前記水平
同期信号に同期した書き込みクロツクを作成する
書き込みクロツク作成回路１４と、 この書き込みクロツクにより前記映像信号が書
き込まれるメモリ回路１８と、 このメモリ回路１８の読み出し用の安定した読
み出しクロツク信号を作成する読み出しクロツク
作成回路２２とを備える時間軸補正回路に於いて
、 前記映像信号入力端子１０と前記メモリ回路１
８間に設けられ前記映像信号を遅延せしめる遅延
回路２４を備えることを特徴とする時間軸補正回
路。[Claims for Utility Model Registration] A video signal input terminal 10, a horizontal synchronization signal separation circuit 12 that separates a horizontal synchronization signal from the video signal applied to the video signal input terminal 10, and from this horizontal synchronization signal separation circuit 12. a write clock generation circuit 14 that generates a write clock synchronized with the horizontal synchronization signal of the memory circuit 14, a memory circuit 18 into which the video signal is written using the write clock, and a stable read clock signal for reading from the memory circuit 18. In the time base correction circuit comprising a readout clock generation circuit 22, the video signal input terminal 10 and the memory circuit 1
8. A time axis correction circuit comprising a delay circuit 24 that is provided between 8 and 8 and delays the video signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989132452U JPH0741265Y2 (en) | 1989-11-14 | 1989-11-14 | Time axis correction circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989132452U JPH0741265Y2 (en) | 1989-11-14 | 1989-11-14 | Time axis correction circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0370476U true JPH0370476U (en) | 1991-07-15 |
| JPH0741265Y2 JPH0741265Y2 (en) | 1995-09-20 |
Family
ID=31679909
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989132452U Expired - Lifetime JPH0741265Y2 (en) | 1989-11-14 | 1989-11-14 | Time axis correction circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0741265Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0267885A (en) * | 1988-09-02 | 1990-03-07 | Victor Co Of Japan Ltd | Jitter cancel circuit |
-
1989
- 1989-11-14 JP JP1989132452U patent/JPH0741265Y2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0267885A (en) * | 1988-09-02 | 1990-03-07 | Victor Co Of Japan Ltd | Jitter cancel circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0741265Y2 (en) | 1995-09-20 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |