JPH037317B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a coding device, and particularly to a device for coding binary image data using a two-dimensional compression code, such as an MR code. It is suitable for use in transmitting image data and storing image data on optical disks, magnetic disks, etc.

[Background of the invention]

MR (modified READ) code is based on CCITT recommendation
T4 has been adopted as a two-dimensional compression code standard for G facsimile equipment. The encoding method is based on each tone change point (the point where the color changes from white to black or vice versa) of the scanning line that is currently being encoded (the above recommendation calls this a coded line, and this specification also follows this). The position of a change point (hereinafter simply referred to as a change point) is encoded according to its relative position to the corresponding change point position of the previous scan line (which the Recommendation refers to as the reference line and is also included herein). This is a sequential encoding method.

FIG. 2 summarizes the rules of MR encoding, and the meanings of the symbols in the diagram are as follows.

a ₀ ...Reference or starting point change pixel on the encoding line.
At the beginning of the encoding line, a ₀ is placed on the virtual white change pixel immediately before the first pixel of the scan line (hereinafter referred to as line).

a ₁ ...The first change pixel to the right of a ₀ on the encoding line.

a ₂ ...The first change pixel to the right of a ₁ on the encoding line.

b ₁ ...Among the changing pixels on the reference line, the first changing pixel to the right of a ₀ and having the opposite color to a ₀ .

b ₂ ...The first changing pixel to the right of b ₁ on the reference line.

In addition, in FIG. 2b, "a ₁ b ₁ = 0", "a ₁ b ₁
An expression such as "=1" indicates that the distance between a ₁ and b ₁ is 0 pixel, 1 pixel, etc., respectively. Also, M
(a ₀ a ₁ ) and M (a ₁ a ₂ ) are MH (modified Huffman) codes corresponding to the number of pixels (run length) from a ₀ to a ₁ and from a ₁ to a ₂ , respectively. , its encoding rules are also specified in detail in CCITT Recommendation T4.

The encoding procedure is roughly divided into three modes. The pass mode is when b ₂ is on the left side of a ₁ , and the sign in this case is uniquely determined regardless of the distance. Horizontal mode is when b ₂ is at the same position as a ₁ or to the right of it, and the distance between a ₁ and b ₁ is 4 pixels or more, and in this case, the signs are a ₀ , a ₁ , and a Determined by the respective distances of ₁ and a ₂ . The vertical mode is other than the above two modes, that is, when b ₂ is
At the same position as a ₁ or to the right of it, and a ₁
This is the case when the distance between and b ₁ is 3 pixels or less, and in this mode, the position of a ₁ is encoded as a relative position from b ₁ . When one encoding process is completed, move a ₀ to position b ₂ if pass mode, a ₂ if horizontal mode, a ₁ if vertical mode, Perform the next encoding process. FIG. 3 is a flowchart representing this encoding procedure.

By the way, in facsimile devices that use telephone lines or low-speed dedicated lines, the information transmission speed of the line is one or two orders of magnitude slower than the processing speed inside the device, so the speed of MR encoding becomes an issue. It won't happen. For this reason, conventional MR encoding has been realized by breaking down the procedure in the flowchart of FIG. 3 into smaller steps and sequentially executing them using a program-controlled microprocessor. Although this method requires less hardware, it cannot be expected to significantly improve the encoding speed. however,
In image processing technologies that are expected to develop in the future, such as high-speed facsimile and image files, it is not only important to research encoding methods with high compression efficiency, but also to increase the speed of the encoding device itself.

[Summary of the invention]

Generally, it goes without saying that converting software to hardware increases processing speed. However, the present invention simultaneously detects change points at a plurality of successive pixel positions of the reference line while synchronously shifting the data of the reference line and the data of the encoded line in their respective processing circuits. The position of a predetermined pixel and the change point detection pixel of the encoding line are matched, and the information of these change points of both lines is supplied in parallel to the encoding sequencer circuit, and the information of the change point of both lines is supplied to the encoding sequencer circuit according to the mutual relationship between them. By determining the encoding mode and making state transitions, a particularly high speed can be achieved.

[Embodiments of the invention]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention. The binary image data source 23 is, for example, a device that scans an optical image and converts it into an electrical signal, such as an imaging device, or a memory that stores original image data. The data is supplied line by line to the image data analysis unit 24 in a bit serial format synchronized with the clock. This image data 34 is added to the encoded line change point detection unit 28 as encoded line data, and is also added to the reference line buffer 27 for use as a reference line for the next line.
Saved in The previous line data that had been stored in the reference line buffer 27 is stored as reference line data 35 as coded line data 3.
4 is applied to the encoded line change point detection unit 28, the reference line change point detection unit 2
9.

The encoded line change point detection unit 28 sequentially tests the encoded line while shifting it, and when a change point is detected, generates an encoded line change point detection signal 45. Further, the reference line change point detection unit 29 shifts the reference line in synchronization with the encoded line, and
The seven successive pixels are simultaneously inspected to detect all change points existing between the seven pixels, and signals 52 to 60 are generated depending on the positions of these change points. The run length counting section 30 receives the encoded line change point detection signal 45 and counts the run length on the encoded line. The MR encoding sequencer unit 31 receives the encoded line change point detection signal 4.
5 and various change point signals 52 to 60 on the reference line.
Based on this, it is determined which of the cases shown in FIG. 2b corresponds to the interrelationships between the various change points, the encoding mode is determined, the MR encoding mode signal 79 is generated, and the state transition is managed. do. Note that this state transition will be detailed later. The MR code output unit 25 that receives the MR encoding mode signal 79 outputs the run length information 68 and 6 of the encoded line as necessary.
9, generates an MR code output 36 and passes it to the MR code storage unit 26.

The clock system management section 32 supplies an input side clock 37 to the data source 23 and the image data analysis section 24, and also supplies an output side clock 38 to the MR code output section 25 and the MR code storage section 26. The scan state management unit 33 provides necessary instructions 39, 109 to the clock system management unit 32 in order to control the operation of the entire device, and also provides instructions 76 for inserting special codes, exceptional processing, etc. Let's do it.

FIG. 4 is a state transition diagram of encoding managed by the MR encoding sequencer section 31. Knowing this state transition is also useful for directly understanding the operation of the entire apparatus shown in FIG. In the figure, state 1 is the initial state. States 2, 3, and 4 represent the states of change point search, change point search, and change point search, respectively, and these are the three types of change point search processing by simultaneous shifting of encoded line and reference line data. correspond to the state. Condition 5
10b is a state in which the MR code corresponding to each case is output in bit series.

When activated from initial state 1 (12), the state transitions to state 2 of change point search. In this state, the data on the reference line and the encoded line are simultaneously shifted and the corresponding change point a ₁ or b ₁ is searched for, and this state remains until a change point appears on either line. When a ₁ is detected, if b ₁ is also detected (13) at the same time, it transits to V(0) output state 5 and outputs V(0) code, and
If b ₁ is detected within 3 bits to the right of a ₁ (that is, a ₁ is within 3 bits to the left of b ₁₎ (14), then V _L (1) to V _L (3)
Transition to output state 6, depending on the distance between a ₁ and b ₁
Outputs either V _L (1) code, V _L (2) code, or V _L (3) code, and if b ₁ is not found within the right 3 bits of a ₁ (15) H output state Transition to 9 and H
Output the sign. On the other hand, if b ₁ is detected (16), a transition is made to state 3 of the change point search.

In state 3 of the change point search, the data of the reference line and the encoded line are shifted simultaneously and the change point is searched accordingly, and this state remains until a change point is detected in either line. However, the target to be searched in this state is the change point a ₁ or b ₂ . When a ₁ is detected, if b ₁ is detected (17) within the left three bits of a ₁ (that is, a ₁ is within the right bit of b ₁ ), then V _R (1) ~ V _R ( 3)
Transition to output state 7, depending on the distance between a ₁ and b ₁
Outputs either V _R (1), V _L (2) code, or V _R (3) code, and if b ₁ is not detected within 3 bits to the left of a ₁ (19) H output state 9 , and outputs the H code. However, if b ₂ is detected (18), it transits to P output state 8 and outputs the P code.

In H output state 9, upon completion of H code output (21), transition is made to M ₀₁ output state 10a, and here, when output of M ₀₁ code is completed (21), transition is made to state 4 of change point search. . In state 4 of the change point search, the data of the reference line and the encoded line are simultaneously shifted again, but in this state, a search for _a2 on the encoded line is performed.
When a ₂ is detected (20), a transition is made to the M ₁₂ output state 10b, where the M ₁₂ code is output.
5 to 8 and 10b When the code output is completed in each output state 21, the state transits to the change point search state 2 again, and the same state transition is repeated until the encoding of one line is completed. . If the line processing is completed (22) at the stage of returning to state 2 of the change point search, the state becomes end state 11, and after that,
It returns to the initial state 1 if necessary.

Next, each part of the apparatus shown in FIG. 1 will be described in detail.
The reference line buffer 27 includes a line buffer (1) 41 and a line buffer (2) 4, as shown in FIG.
2 is switched by a selector 111, and while the encoded line data 34 currently being encoded is being written to one buffer, the data of the previous line is read from the other buffer as reference line data 35. be done. Although these write and read operations are not shown, they are performed in bit series in synchronization with the input side clock 37. Note that switching between buffers (1) and (2) is performed at the time when one line of encoding processing is completed.

FIG. 6 shows the configuration of the encoded line change point detection section 28. The encoded line data 34, which arrives in bit series, is shifted over the latches 43-1 and 2 one bit at a time, and if there is a change point, the output of the exclusive OR gate 44 becomes "1" due to the mismatch between the outputs of both latches. ” becomes. This "1" output is nothing but a signal representing a changing point on the encoded line. The signal representing this change point is shifted on the latches 43-3 to 43-5 and then output as the encoded line change point detection signal 45. Therefore, the encoded line change point detection signal 45 becomes "1" when the change point on the encoded line reaches the output of the latch 43-5, and becomes "1" when the other pixels reach there. This is a string of binary signals with a value of 0''. However, the change points detected here alternately include both white->black change points and black->white change points. Shifting through the latches is also controlled by an input clock 37, not shown. The reason why the change point signal is delayed by three stages of latches 43-3 to 43-5 is in the reference line change point detection section 29, which will be described below.
7 by delaying the change point signal through 6 latches.
This is to synchronize the timing with the reference line change point detection signal output from the third latch at the center when detecting change points across pixels simultaneously.

The configuration of the reference line change point detection section 29 is as shown in FIG. Reference line data 35 supplied in bit series is shifted over latches 43-6 and 7, and is passed through an inverter 46a and an AND gate 47a.
The change points are detected by the inverter 46b and the AND gate 47b. The output 50 of the AND gate 47a is a binary signal string that becomes "1" at the black→white transition point and "0" at other pixel positions, and is sequentially shifted over the latches 43-8 to 43-13. Furthermore, the output 51 of the AND gate 47b is
The latch 43-1 is a binary signal string that is "1" at the point of change from white to black and "0" at other pixel positions.
4 to 19 are sequentially shifted. Note that all of these shifts are performed under the control of the input side clock 37. The selectors 48-1 to 48-7 select whether to output the black→white change point signal 50 or the white→black change point signal 51 as the change point signals 52 and 55 to 60, according to the selection signal 61. The selection signal 61 is transmitted to the MR encoding sequencer section 31, which will be described later.
(Figure 9). In addition, selector group 4
The connection positions on the input side are reversed between 8-1 to 48-4 and 48-5 to 7. Therefore, between both selector groups, under the same selection signal 61, the signal 5
If the selections for 0 and 51 are reversed, with the white→black transition point signal being selected on the one hand, the black→white transition point signal is being selected on the other hand. The reason for this connection is as explained in Figure 2.
This is because b ₁ and b ₂ are change point pixels in opposite directions.

The output 52 of the center selector 48-4 indicates whether or not the center pixel of the seven successive pixels tested by this circuit is a change point, and its position on the line is determined by the sign, as described above. This corresponds to the position of the pixel that generates the line change point detection signal 45 (FIG. 6). This change point signal 52 is used as a reference line change point detection signal. Selector 48-
The output 55 of 1 is a signal (right third bit change point signal) indicating whether or not the pixel 3 bits to the right of the reference line change inspection position 52 is a change point. In addition,
Here, all references to right and left refer to Figure 2a. In FIGS. 6 and 7, the line data is supplied first to the bit of the pixel on the left side of FIG.
It should be noted that the left and right sides are reversed from the representation in Figure a. Similarly, signal 56 is the right second bit change point signal, and signal 57 is the right first bit change point signal. The change point signals 55 to 57 are
The signals are collected by the OR gate 49b to form a right three-bit change point signal 54. On the other hand, selector 48-5
~7 outputs become the left first to third bit change point signals 58 to 60, respectively, and these are OR gate 4.
The change point signal 53 in the left 3 bits is collected at 9a.
form. These change point signals 53 to 60 are
At the time when the encoding line change point detection signal 45 becomes "1", it is interpreted as a signal representing whether or not b ₁ exists on the right or left bit of a ₁ , and is sent to the MR encoding sequencer section. This causes 31 state transitions (Fig. 4). For example, in state 2 of the change point search, the moment when the encoded line change point detection signal 45 becomes "1" (the change point of this encoded line is the same as the pixel that produces the output 52 in FIG. 7 as described above). position), and the right second bit change point signal 56 is “1”, the right second bit of _a1
There is b ₁ (in other words, there is a ₁ in the second left bit of b ₁ ), and the transition to state 6 (14)
is performed, and a V _L (2) code is output.

FIG. 8 shows the configuration of the run length counting section 30. Encoding line run length counter 62
is cleared by the clear signal 67, and thereafter,
Each time the input side clock 37 shifts the encoded line data by one bit, the count is increased. The clear signal 67 is the output of the OR gate 64, and the inputs to the OR gate 64 are the MH code output end signal 93 from the MR code output section 25 (FIG. 10) and the run length counter clear signal 66. As will be described later, the signal 93 is generated at the end of the output of each code of M ₀₁ and M ₁₂ in the horizontal mode, and the signal 66 is generated at the end of the output of each code of _M 01 and M 12 in the horizontal mode, and the signal 66 is generated at the end of the output of each code of M ₀₁ and _M 12 in the horizontal mode. )〜V _R
(3) and occurs at the end of outputting each code of P. Therefore, the encoded line run length counter 62
is cleared every time a change point occurs on the encoded line, and during that time the input side clock 37
In the end, the encoded line run length counter 62 counts the number of white and black pixels that continuously exist on the encoded line. However, the clear signal at the end of P code output is output at the time when b ₂ is detected on the reference line, and in this case, the encoding line run length counter 62 clears the code on the right side of the b ₂ position. The number of white and black pixels consecutively existing on the color line is counted. The count value of the encoded line run length counter 62 is used as a run length value 68 when the MR code output unit 25 generates M ₀₁ and M ₁₂ codes. The encoding line monochrome flip-flop 63 is inverted every time the encoding line change point detection signal 45 becomes "1". However, this signal 45 becomes "1" at each change point from white to black and from black to white. Therefore, the output of this flip-flop 63 is the output of the run length counter 62.
indicates whether the pixel block being counted is black or white, and is used as the encoding line black and white flag 69.

The configuration of the MR encoding sequencer section 31 is shown in FIG. The MR encoding state management ROM 71 and the MR encoding state holding latch 72 constitute a sequencer, which manages the state transitions explained in FIG. 4. Please also refer to Figure 4 below. The MR encoding state holding latch 72 is a 2-bit latch and holds states 2 to 4 of the change point search. That is, the latch state "00" indicates state 2 of the change point search, "01" indicates state 3 of the change point search, and "10" indicates state 4 of the change point search. During input to the MR encoding state management ROM 71, the encoding line change point detection signal 45 is “1”
If , it is "a ₁ detection" or "a ₂ detection", and if the reference line change point detection signal 52 becomes "1",
"b ₁ detection" or "b ₂ detection". If the left 3-bit change point signal 53 is "1" when the encoded line change point detection signal 45 becomes "1", it means "b ₁ is within the left 3 bits of a ₁ ". Similarly, if the change point signal 54 within the right three bits is "1", it means "b ₁ within the right three bits of a ₁ ".
The MH code forced output signal 76 is normally "0", and this signal will be described later.

These input signals 45, 52, 53, and 54 to the MR encoding state management ROM 71 change sequentially as the encoded line data 34 and reference line data 35 shift, and in response, the MR encoding state management ROM 71 changes. , updates the state of the MR encoding state holding latch 72, and generates various control signals. That is, if condition 16 in FIG. 4 is satisfied,
Update the state of the MR encoding state holding latch 72,
When the same condition 13, 14, 15, 17, 18 or 19 is satisfied, the VPH code output request signal 77 is generated and the VV corresponding to the specific content of the condition is generated.
(0) HP selection signal 81 (2 bits), V _L , V _R
If the same condition 20 is satisfied, the M ₁₂ output request signal 78 is generated. When state transition conditions 13, 14, 16, 18, and 19 are satisfied, the signal 80 is generated because it is necessary to switch the direction of the searched change point (white → black or black → white) on the reference line. Then, the black-and-white/black-and-white change point selection flip-flop 73 is inverted. The output of this flip-flop 73 is sent to the selector 48--in FIG.
Switch between 1 and 7.

The MR encoding mode latch 74 is a group of latches that specifically indicates to which case the mutual relationship between changing points corresponds to the encoding rule of FIG. 0) Consists of HP selection signal 81, V _L and _VR selection signals 82, and change point distance data 83 which is the output of selector 75. The selector 75 converts the right first to third bit change point signals 57 to 55 or the left first to third bit change point signals 58 to 60 supplied from the reference line change point detection section 29 in FIG. Switching is performed according to _{the L} , _VR selection signal 82. These data are set
The state of the MR encoding mode latch 74 is shown in FIG.
Symbol P, HM ₀₁ M ₁₂ , V (0), V _R (1) ~ V _R (3), V _L
(1) to V _L (3), which indicates which code should be output, and the MR encoding mode signal 7
9, it is supplied to the MR code output unit 25, which will be described next.

The configuration of the MR code output section 25 is shown in FIG. The VPH code output ROM 84 has symbols P, H, V (0), V _R (1) to V _R (3), V _L (1) to
It holds the code corresponding to each of V _L (3),
The code to be output is selected according to the MR encoding mode signal 79, and the VPH code output counter 8
As the count of 5 increases, bits are output in series as VPH code output data 97. The VPH code output counter 85 is enabled by a VPH code output mode flag 94 supplied from the clock system management unit 32 described below, counts the output side clock 38, and outputs the VPH code which is the output of the VPH code output ROM 84 itself. Cleared by end signal 91. The VPH code output ROM 84 also generates a run length counter clear signal 66 and an M ₀₁ output request signal 92. The run length counter clear signal 66 is P, V (0), V _L (1) to V _L (3),
It is generated when the output of each code V _R (1) to V _R (3) is completed, and clears the encoded line run length counter 62 in FIG. Furthermore, the M ₀₁ output request signal 92 is generated when the output of the H code (001) is completed, and is generated by the clock system management section 32 as described in the next section.
Derive the M ₀₁ output mode flag 95 via
It controls the MH code output ROM 86 which will be described next.
Note that the VPH code output end signal 91 mentioned above is
Occurs simultaneously with each occurrence of signals 66 and 92.

The MH code output RMO 86 holds the MH code table specified in CCITT recommendation T4, and outputs the code according to the run length value 68 and the encoded line monochrome flag 69 supplied from the run length count section 30 in FIG. The exponent MH code is selected and output in bit series as MH code output data 98 (M ₀₁ or M ₁₂ ) as the MH code output counter 87 counts up. This MH code output counter 87 is enabled via an OR gate 89 by an M ₀₁ output mode flag 95 or an M ₁₂ output mode flag 96 generated by the clock system management section 32, which will be described later, and counts the output side clock 38. MH code output This is the output of the ROM86 itself.
It is cleared by the MH code output end signal 93. This signal 93 is generated when the transmission of the M ₀₁ code is completed.
Occurs when the _M12 code has been sent. selector 8
8 converts either the VPH code output data 97 or the MH code output data 98 into the MR code output data 36.
Select as. This selection is controlled by the output of an OR gate 90 that receives the aforementioned M ₀₁ output mode flag 95 and M ₁₂ output mode flag 96.
If either mode flag 95 or 96 is "1", MH code output data 98 is selected; otherwise, VPH code output data 97 is selected. The selected MR code output data 36 is written into the MR code storage section 26 in bit series.

FIG. 11 shows the configuration of the clock system management section 32. The output of main clock generator 108 is
Through one of the AND gates 106 or 107,
They serve as an input side clock 37 and an output side clock 38, respectively. These AND gates are controlled by an encoding execution flip-flop 99 and three mode flip-flops 101-103.

When the encoding execution flip-flop 99 is set by the line encoding start signal 109 given from the scan state management section 33, it sets the first control inputs of the AND gates 106 and 107 to "1", and
Prepare clock transmission. The line end determination counter 100 is first set with the number 39 of bits (pixels) constituting one line from the scan state management section 33, and is counted down by the input side clock 37. On the other hand, the VPH code output mode flip-flop 101 is set by the VPH code output request signal 77 supplied from the MR encoding sequencer section 31 in FIG. 9, and sets the VPH code output mode flag 94 to "1". Figure 10
It is reset by the VPH code output end signal 91 supplied from the MR code output section 25. The _M01 output mode flip-flop 102 is shown in FIG.
It is set by the _M01 output request signal 92 supplied from the MR code output section 25, and the _M01 output mode flag 95 is set to "1", and the MR code output section 2
It is reset by the MH code output end signal 93 supplied from 5. Furthermore, the _M12 output mode flip-flop 103 receives the _M12 output request signal 7 supplied from the MR encoding sequencer section 31 in FIG.
_M12 output mode flag 9
6 as “1” and the MH code output end signal 93
It is reset by . "1" of the VPH code output mode flag 94 corresponds to states 5 to 9 in FIG. 4, "1" of the M ₀₁ output mode flag 95 corresponds to state 10a, and "1" of the M ₁₂ output mode flag 96 ” corresponds to the same state 10b. These flags 94 to 96 are given to the MR code output section 25 to control the code output operation as described above.

Immediately after the start of encoding, these flags 94 to 96
are all “0”, so OR gate 10
The output of 4 is also "0". As a result, the AND gate 106 is turned off, and the output side clock 38 is turned off.
is inhibited, and on the other hand, AND gate 107 is turned on via inverter 105, and input side clock 37 is generated. As the processing progresses and a change point is detected and it is time to generate some code output, one of the flags 94 to 96 becomes "1", and as a result, the AND gate 107 is turned OFF and the input side clock 37 is turned off. Interrupted, AND instead
Gate 106 turns on, output side clock 3
8 is generated. When the code output ends, the corresponding flag returns to "0", the output clock 38 stops, and the input clock 37 resumes outputting.

By repeating the above process, the image data analysis unit 24
When the shift of one line in is completed, the count value of the line end determination counter 100 becomes "0". After that, the output of the last symbol is finished and
When the VPH code output end signal 91 or the MH code output end signal 93 becomes "1", the OR gate 111
The output of AND gate 112 becomes "1", and the output of AND gate 112 resets encoding execution flip-flop 99. As a result, AND gates 106 and 107 are both turned OFF, and the output of clocks 37 and 38 is stopped. Further, the output of the AND gate 112 is sent to the scan state management section 33 as a 1-line encoding end signal 110.

As described above, the scan state management unit 33 in FIG. 1 supplies the line encoding start signal 109 and the number of bits per line information 39 to the clock system management unit 32. A line encoding end signal 110 is received. In addition, the scan state management unit 33 adds a predetermined EOL (End Of Line) code 40 before starting processing of each line.
Write to the MR code storage section 26.

The scan state management section 33 can also send the MH code forced output signal 76 to the MR encoding sequencer section 31 in FIG. 9 to forcibly change the encoding process of one line to MH encoding. . 9th
In the figure, the MH code forced output signal 76 is “1”
Then, the state of the MR encoding state holding latch 72 is set to "10", that is, state 4 of the change point search in FIG. 4, and is fixed. In this state, M ₁₂ output state 10 due to a ₂ detection (20)
The process moves to b, and returns to state 4 again after the _M12 output is completed.
As a result, only the _M12 code is output in response to the detection of successive change points on the encoded line, so one line of data is encoded only with the MH code. CCITT Recommendation T4 requires K-1 lines to be MR
It is specified that one line is MH encoded each time encoding is performed, and the constant K is called a parameter K.

The operation of the scan state management unit 33 is performed at a relatively low speed because the period is the encoding processing time of one line. Therefore, this part does not require any special ingenuity in its configuration, and may be realized by a program-controlled microprocessor.

〔Effect of the invention〕

According to the present invention, compared to processing by a microprocessor, it is possible to achieve a significant speedup that goes beyond the general speedup achieved by converting software to hardware.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the overall configuration of an embodiment of the present invention, and Fig. 2 shows image data and
3 is a flowchart of the basic procedure of MR encoding, FIG. 4 is a state transition diagram of encoding according to the present invention, and FIG. 5 is a block diagram of the reference line buffer in FIG. 1. 6 is a block diagram of the encoded line change point detection section, FIG. 7 is a block diagram of the reference line change point detection section, FIG. 8 is a block diagram of the run length count section, and FIG. 9 is a block diagram of the coded line change point detection section. Similarly, the block diagram of the MR encoding sequencer section, Figure 10, is the same.
Block diagram of MR code output section, 11th
The figure is also a block diagram of the clock system management section. 28... Encoding line change point detection unit, 29...
Reference line change point detection unit, 30... Run length counting unit, 31... MR encoding sequencer unit,
25...MR code output section.

Claims (1)

[Claims] 1 Apparatus for sequentially encoding the position of each tone change point of a scan line currently being encoded according to its relative position with respect to a corresponding tone change point of a reference line, i.e., the immediately preceding scan line, comprising: , a reference line processing circuit that simultaneously detects change points at a plurality of successive pixel positions while shifting reference line data in bit series; and a reference line processing circuit that shifts encoded line data in bit series in synchronization with the shift of reference line data. An encoding line processing circuit detects the change point at a pixel position corresponding to a predetermined one of the plurality of successive pixels of the reference line, and simultaneously receives information on the change point detected by both of these circuits. and an encoding sequencer circuit that determines an encoding mode and performs state transition according to their mutual relationship.