JPH0374078B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention selectively receives still image information signals such as characters and patterns that are multiplexed and transmitted during the vertical retrace period of a video signal, sequentially records them in parallel in a memory, and reads out the contents of the memory at high speed. The present invention relates to a still image information reading circuit suitable for a main memory and its reading circuit of a television multiplex teletext receiver that displays still image information on a picture tube. In particular, the purpose is to use memory efficiently. The television multiplex character transmission system uses C proposed by NHK.
Various methods have been proposed, including a method called a packet method. This method uses one horizontal scanning period (for example, 20H and 283H) during the normal vertical retrace period to multiplex transmit one line of characters, patterns, etc. on the screen. In the case of graphics, 18 lines are used as one block, and in the case of figures, 26 lines are used as one block. Between each block, control signals for one line [following one
In addition to the code that indicates which line on the screen a block (usually 15 characters) corresponds to, there is also a color code (90 bits) that determines what color each half of the 15 characters should be displayed in. including). First, an overview of a television multiplex character transmission system receiver to which the present invention is applied will be explained below with reference to FIG. In FIG. 1, the parts constituting a normal television receiver are omitted, and only the character and pattern information reproduction system is shown. A composite video signal (output of a video detection circuit) in which character and pattern information are multiplexed is applied to the input terminal 1. The composite video signal passes through a waveform shaping circuit 2 and is applied as an input to a signal sampling circuit 3 which extracts multiplexed information and signals related thereto during the 20th and 283rd horizontal scanning periods during its output. The signal extraction circuit 3 counts the output of the synchronization separation circuit 4 and the horizontal synchronization signal, and responds to the output of a sampling pulse generation circuit 5 that generates pulses for extracting the 20H and 283H signals from the count output. extracts the multiplexed information signal and sends the signal to the buffer memory 6, line code comparison circuit 7, program code comparison circuit 8 and STX detection circuit 9.
applied to each input. The line counter 10 is driven by a horizontal synchronizing signal and provides its output to the line code comparison circuit 7 as another input. The program code comparison circuit 8 receives the program code designated by the program designation switch 11 that selects the program to be multiplexed and transmitted, and compares it with the program code given as another input from the signal sampling circuit 3. be compared. The comparison output is provided by a control circuit 1 that allows a CPU, etc.
2, the information to be written to the buffer memory 6 is specified. STX included in the control code and detected by the STX detection circuit 9 during the output of the signal extraction circuit 3
The signal is input to the clock pulse generation circuit 13 as a control signal. The clock pulse generation circuit 13 receives the output of a subcarrier generation circuit 14 that generates a signal corresponding to a color subcarrier based on a color burst signal separated from a composite color video multiplexed signal applied to the input terminal 1, A clock pulse is generated at a frequency 3/5 times that of the carrier wave signal fsc and whose phase coincides with the starting edge of the STX signal. When the program code comparison circuit 8 detects a match between the designated program code (output of the program designation circuit 11) and the program code in the sampling signal, the detection output is provided to the control circuit 12. Similarly, when the line code comparison circuit 7 detects a match between the line code in the multiplexed signal and the line counter 10, the detection output is also sent to the control circuit 12.
added to. Therefore, in the control circuit 12,
After confirming that both the program code and line code match the specified code, open the rewrite gate 15,
The contents of the buffer memory are transferred to the main memory 20. Reference numeral 16 indicates a signal processing circuit that reads out the contents of the main memory 20 and applies it to the CRT 17 as a video signal. If the main memory 20 is constituted by a shift register or the like, it will be expensive including peripheral circuits and will require a considerable amount of space, so it may be considered to replace it with a dynamic RAM. Figure 2 shows a block diagram of the main part of an example of this.
Refresh memory for patterns PM1, PM
2. PM3 and PM4, a parallel/serial conversion circuit (P-S) that allows a shift register to convert parallel input from each refresh memory into serial input (character signal output), and a 256-bit refresh memory each. Refresh memory CM1, CM for 4 color codes (4-bit parallel data) consisting of
2. Read the outputs of CM3 and CM4 and each refresh memory, temporarily hold them, and output them in synchronization with the output of the parallel-to-serial conversion circuit (P-S);
It consists of a latch circuit LT that applies voltage to the gate circuit (included in the signal processing circuit) provided for each RGB color, and an address signal generation circuit AD for writing and reading. Although the write address signal generation circuit is not particularly shown, it sequentially sends serial input pattern data to 1 bit PM1-PM2-PM3-PM4-PM1-
Any configuration may be used as long as it generates an address signal that is cyclically written and stored in the refresh memory for each pattern, such as PM2-PM3-PM4, . . . The color code specifies one color using 3 bits, and is 1/
Eight colors can be specified in units of two characters. After the unit color designation bits are serially converted, they are stored in refresh memories CM1 to CM3 (CM
The write address data generation circuit is omitted because it is sufficient to designate the addresses so that they are sequentially written to (4 is used preliminarily). The main memory 20 is configured as described above, and the read address signals _A0 to _A5 are generated by the horizontal address counter HA which receives the clock pulse fc as input.
A ₆ to _{A 13} are created using a vertical address counter VAD that receives the horizontal synchronization signal HD as input, and the address signal for color code reading is created using a separate horizontal synchronization signal HD (since the vertical address signal for reading color data cannot be shared). By creating a color data counter VCA with the input color data counter VCA and sequentially specifying the addresses of each memory, each pattern PM1, PM1, A total of 4 bits of patterns read out in parallel simultaneously from PM2, PM3 and PM4 can be serially read out and taken out as character and pattern signal outputs, and at the same time color (code) memories CM1, CM2 and CM3 can be read out in series. The code is read out from , the latch circuit LT holds it for 1/2 character period, and the output is synchronized with the output of the serial/parallel conversion circuit to the gate circuit for creating each RGB signal in the signal processing circuit 16 (for example, By adding it as a gate signal to an AND gate), a color character or pattern signal can be obtained. Since the color code requires 3 bits for 8 bits of pattern data, the lowest signal _A0 of the address for pattern memories PM1-PM4 is not necessary. The color code is Color Memory CM1 ~
Each time the pattern memories PM1 to PM4 are read twice, each of the pattern memories PM1 to PM3 is read out once. Even if the pattern signals are read out sequentially and the next line is moved, the pattern information remains 1.
Since it is necessary to extract the same color code as long as it corresponds to one block, the vertical address is created separately as described above. In other words, the color address counter VCA uses the horizontal synchronization signal HD
After dividing the frequency by 26, the 3 bits A' ₆ to A' ₈ specify colors for a total of 8 lines (26 x 8). Configuring the main memory 20 as described above has some merits, but (a) it requires a memory dedicated to color codes in addition to the refresh memory for patterns, and (b) it makes it difficult to access each memory using different address data. Since it is necessary to do this, the circuit becomes unavoidably complicated, and (c) memory usage efficiency is required. In the present invention, further consideration is given to this point, and the above-mentioned main memory 20 is configured as shown in FIG. 3. That is, the memory group M is a refresh memory (dynamic RAM) M in units of 8K bits.
1, M2...M7, M8, and out of a total memory capacity of 64K bits, about 50K bits are secured as a pattern memory area, and the remaining 14K bits are used as a color code memory area (M6, M8 in the embodiment).
7 and M8 memory), it is possible to eliminate the need for some of the color code dedicated memories CM1 to CM4 and their peripheral circuits (such as the address data (code) generation circuit) in the example shown in Figure 2. It is something to do. The writing of character and pattern information into each memory M1 to M8 is basically the same as in the case shown in FIG. , sequentially 1 bit at a time M1-M2-M3-M4-M5-M
6-M7-M8→M1-M2...M7-M8 are sequentially written and stored in the corresponding addresses of each memory. Other than these points, the write address data generation circuit has no special features, so a detailed description thereof will be omitted. The parallel 8-bit outputs of each of the memories M1 to M8 are read out in an access time of fc/8 to fc/4, and are supplied to a parallel-to-serial converter circuit PSC that allows an 8-bit shift register that can be preset in parallel, and is , converted to a character signal. The parallel-serial shift register PSC is connected to an address data generation circuit ADG using fc (≒5.73MHz) as a clock pulse.
The output of the 8 frequency divider circuit FD8 is used as a load pulse LP, and as a result, character and pattern data are read from the memory groups M1 to M8 at 8 times the speed and added as a serial signal to the subsequent signal processing circuit 16. Next, the address signal generation circuit ADG for reading out characters, patterns, and color codes in common will be explained. In order to read data from memory groups M1 to M8, 13-bit address signals _A0 to _A12 are applied via the address bus. In this embodiment, since an 8-bit parallel readout method is adopted, the frequency of the address signal is fc/8 (=f _SB /5). Even cheap dynamic RAM will work well if the access time is 4/fc. The address signal generation circuit ADG consists of a divide-by-8 circuit FD8 which receives the clock pulse fc as an input, a horizontal address counter HAC which accepts a quinary counter as its input, and a 26-decimal (26-decimal) circuit which receives the horizontal synchronization signal HD as an input. Vertical address counter consisting of 5 bits) + octal (3 bits) cascaded counter
A ₀ obtained from VAC and the output of the divide-by-8 circuit
, and an OR circuit OR which takes the logical sum of the address signals A' ₅ to A' 9 of the 26-decimal counter of the vertical address counter VAD, and the address signals A ₀ to A' ₉ of the vertical address counter VAD. _A4 is taken out from the horizontal address counter HAC, _A5 to _A9 are taken out from the OR circuit OR, and _A10 to _A12 are taken out from the subsequent octal (3-bit) counter of the vertical address counter VAC. By the way, since the color code requires 3 bits for the 8-bit character pattern as described above, it is clear that no switching is required for the horizontal address when reading both data. However, it is essential to switch the vertical address when reading a pattern and when reading a color code. The vertical address counter VAC is configured to generate address signals _A'5 to _A'9 using a hexadecimal counter (5 bits), so it is not suitable for reading characters or patterns.

[0] ₁₀ ~ [25] Use only ₁₀ ,
[26] ₁₀ to [31] ₁₀ are not used for pattern memory reading. Therefore, if the color code is stored in an address that satisfies A ₅ to _{A 9} ≡1, it is possible to always read the color code of the corresponding line when reading character or pattern information of a certain line. . In short, at the timing when the color code is to be read, only the address signals _A5 to _A9 need to be separated from the counter output so that they become logic [1]. Therefore, two D-flip-flops D ₁ and D ₂ are connected in cascade to each color code data line of a latch circuit LTH that temporarily holds a color code readout output, and an address signal such as A ₀ is applied to the flip-flop as shown in FIG. 5A. ₀₁ , A ₀₂ , the color code is read out in the first half 4/fc time, the pattern information is read out in the second half 4/fc time, and the former is used as a latch circuit.
The signal is input to each D flip-flop _D1 of the LTH, and the latter is input in parallel to the parallel-to-serial conversion circuit PSC. The color code read out as described above is read into D1 by the latch circuit LTH using a load pulse (LD ₂ ) which is 180° out of phase with the load pulse LD ₁ taken out as the output of the divide-by-8 circuit FD8. After being temporarily latched for approximately 8/fc time, it is shifted synchronously with the parallel/serial conversion circuit PSC by the load pulse LD ₂ to form a part of the signal processing circuit 16.
By applying voltage to the RGB gates Gr, Gg, and Gb, respectively, the output (corresponding pattern or character signal) of the parallel-to-serial conversion circuit PSC is converted into a color signal specified by the color code. Figure 4 shows a method that is an improved version of the so-called telescan method, which is based on horizontal scrolling, and which enables full-screen display by loading character pattern information and color code information into the main memory of a character multiplex TV receiver. When reading this, the output address signal of the vertical address counter VAC (8-bit binary counter) is switched and supplied to the main memory 20, and both pieces of information are read out synchronously from the same memory group, converted into parallel to serial at high speed, and read out. An example is shown. As is well known, in the improved telescan system, one line consists of 16 lines, and one screen consists of 13 lines. Therefore, the vertical address counter is a complete binary counter formed by 8 bits _A5 to _A12 .

[0] ₁₀ to [255] Among _{the 10} address signals,

[0] ₁₀ to [207] ₁₀ will be used to memorize the pattern. Since 16 lines constitute one unit, the color code is used as the bit information, taking into account that A ₉ to _{A 12} can be considered to represent the row (unit) number. Then, during the color code reading time, that is, before reading the pattern information, the address signal terminals _A9 to _A12 of the vertical address counter are switched to _A5 to _A8 ,
Further, all signal outputs of A ₉ to _{A 12} are set to logic [1].
If the address signal applied to the vertical address counter VAC is switched and read as described above, vertical addresses _A5 to _A12 are created.

[0] ₁₀
~ [255] out of ₁₀

[0] ₁₀ to [207] ₁₀ are used to store pattern data, the color code for the first line is [240] ₁₀ , and the color code for the second line is [241] _10.
If the color code on the 13th line is stored in [252] ₁₀ , then the color code in the 13th line will be stored in memory M1 as in the embodiment shown in Fig. 3.
~M8 can be used efficiently. As described above, according to the present invention, the refresh memory group M1 to M8 constituting the main memory is divided into at least two areas, A (character and pattern storage area) and B (color code area). By switching the address signal to read out the data in area B while reading out the information in B and serially converting it,
Memories that used to be provided separately (such as character pattern memory and color code memory, which required multiple groups) can now be replaced with one group of memories, and peripheral circuits such as address signal generation circuits can be simplified. It is possible to enjoy the effects. In the above explanation, the main memory of "NHK C method", "packet method", or "improved telescan method" was targeted, but it is also applicable to reading of memory of "Teletext" and other methods that use character codes together. Needless to say, it can also be applied.

[Brief explanation of drawings]

FIG. 1 is a block diagram of main parts of a character multiplex television receiver to which the present invention can be applied;
The figure is a block diagram of a conventional main memory and peripheral circuits, FIG. 3 is a block diagram of a main memory and peripheral circuits of the present invention, FIG. 4 is a block diagram of main peripheral circuits of another embodiment, and FIG. , is an operation explanatory diagram. M1 to M8...Refresh memory, PSC...
Parallel-to-serial conversion circuit, LTH...latch circuit, ADG...
...address signal generation circuit, G...gate circuit.

Claims (1)

[Scope of Claims] 1. At least a pattern area A that stores pattern information and a color code area B that stores a color code that specifies the color of each line of this pattern information are specified in N memories M. ₁ ～ _M8
and horizontal address signals A ₀ to _{A 4} of the N memories.
a horizontal address counter HAC that specifies the vertical address signals _A5 to _A12 of the N memories;
a vertical address counter VAC that specifies the above-mentioned pattern area A; a parallel-to-serial conversion circuit PSC configured to input each of the N memory outputs in parallel, convert them serially at N times the speed and output pattern information; While the pattern information is read from each of the memories and serially converted by the parallel-to-serial conversion circuit PSC, a part of the vertical address signal is used to switch the address signal to an address signal corresponding to the color code area B. _A5 ～ _A9 ,
_A9 to _A12 are set to values specifying the color code area B, and the remaining values of the vertical address signals _A10 to _A12 and _A5 to _A8 are set to the output _A5 of the vertical address counter VAC. ~ _A12 , the address signal switching circuit ADG has outputs _A10 ~ _A12 , _A9 ~ _A12 counted for each row, and the color code area read out by the switched address signals. a latch circuit LTH that latches the color code information of B; an output circuit Gr that outputs a color signal designated by the color code based on the color code information from the latch circuit LTH and the pattern information from the parallel-serial conversion circuit PSC; A still image information readout circuit comprising Gg, Gb, and.