JPH0374963U - - Google Patents
Info
- Publication number
- JPH0374963U JPH0374963U JP13826489U JP13826489U JPH0374963U JP H0374963 U JPH0374963 U JP H0374963U JP 13826489 U JP13826489 U JP 13826489U JP 13826489 U JP13826489 U JP 13826489U JP H0374963 U JPH0374963 U JP H0374963U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- print head
- outputs
- higher order
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012795 verification Methods 0.000 claims description 3
- 238000013524 data verification Methods 0.000 claims 1
- 238000001514 detection method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Accessory Devices And Overall Control Thereof (AREA)
- Dot-Matrix Printers And Others (AREA)
Description
第１図は本考案の一実施例を示すブロツク図で
ある。
１……上位システム、２……インタフエースコ
ントロール回路、３……上位信号入力回路、４…
…メカコントロール回路、５……印字ヘツド入力
回路、６……印字ヘツド、７……同期回路、８…
…照合回路、９……判定回路、１０……表示回路
。
FIG. 1 is a block diagram showing one embodiment of the present invention. 1... Upper system, 2... Interface control circuit, 3... Upper signal input circuit, 4...
...Mechanical control circuit, 5...Print head input circuit, 6...Print head, 7...Synchronization circuit, 8...
. . . Verification circuit, 9 . . . Judgment circuit, 10 . . . Display circuit.
Claims (1)
位信号として出力する上位信号入力回路と、印字
ヘツドに出力する信号データを取り込んで印字ヘ
ツド信号として出力する印字ヘツド信号入力回路
と、前記上位信号と前記印字ヘツド信号との同期
をとる同期回路と、前記上位信号と前記印字ヘツ
ド信号に含まれる印字データを照合して照合結果
を出力する印字データ照合回路と、前記照合結果
を判断し判断結果を出力する判定回路と、前記判
定結果に応じて表示する表示回路を含むことを特
徴とする誤印字検出回路。 A higher order signal input circuit that takes in print data from the host system and outputs it as a higher order signal, a print head signal input circuit that takes in signal data to be output to the print head and outputs it as a print head signal, and a higher order signal and the print head. a synchronization circuit that synchronizes with the signal; a print data verification circuit that compares the print data included in the upper signal and the print head signal and outputs a verification result; and a determination circuit that determines the verification result and outputs the determination result. A printing error detection circuit comprising: a circuit; and a display circuit that displays a display according to the determination result.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13826489U JPH0374963U (en) | 1989-11-28 | 1989-11-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13826489U JPH0374963U (en) | 1989-11-28 | 1989-11-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0374963U true JPH0374963U (en) | 1991-07-26 |
Family
ID=31685374
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13826489U Pending JPH0374963U (en) | 1989-11-28 | 1989-11-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0374963U (en) |
-
1989
- 1989-11-28 JP JP13826489U patent/JPH0374963U/ja active Pending
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