JPH0375699U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an address generation device for a digital delay device which is an embodiment of this invention, Fig. 2 is a waveform diagram of the latch signal of the element shown in Fig. 1, and Fig. 3 is the circuit shown in Fig. 1. FIGS. 4a and 4b are waveform diagrams for explaining an example of the conventional technology. 1...Target value register, 2, 3...Register, 4...
Comparator, 5... Selector, 6... First adder, 7...
Current value register, 8...second adder, 9...subtraction counter.

Claims (1)

[Claims for Utility Model Registration] 1. A target value register that stores a target value of delay time, a current value register that stores the current delay time, and a comparator that compares the contents of the target value register and the current value register. , positive based on the output of the comparator,
a selector that selects and outputs three types of numbers, zero and negative; a first adder that adds the output of the selector to the contents of the current value register; a counter that outputs the absolute address of the digital delay device; The second one adds the contents of the counter and the contents of the current value register.
The contents of the current value register are updated by the output of the first adder, and the contents of the updated current value register and the output of the counter are added by a second adder to generate a digital signal. An address generation device for a digital delay device configured to output a delayed address of the delay device. 2. The address generation device for a digital delay device according to claim 1, wherein the contents of the target value register are set by a microcomputer.