JPH0376059B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a data transmission device that performs loop switching in a loop data transmission system.

Prior Art In a loop data transmission system, signals in the opposite direction are transmitted in consideration of failures in the transmission path2.
A book transmission path may be arranged. Generally, only one transmission line is used, and if there is a failure in the transmission line in use, the other transmission line is used. Conventionally, this type of loop switching was performed using a "master control station"
It is called a "center station," and when it identifies a clock signal disconnection, it sends a special command to the master station through the standby system, and the master station uses a separately wired line to switch between each station under the control of a special control device. It has been carried out. This type of system has the disadvantage that if a failure occurs in the special control device, it may develop into a fatal failure, and that an extra special line is required.

Purpose of the Invention The purpose of the present invention is to automatically detect the section where the failure occurred when a failure occurs in the active and standby transmission paths between certain data transmission devices, without being aware of the particular data transmission device. It is an object of the present invention to provide a data transmission device which forms a return loop (loop back) in a state where the data transmission device is removed.

Configuration of the Invention The device of the present invention includes two parallel loop-shaped transmission paths in which signals flow in directions opposite to each other, and a plurality of data transmission devices connected to both of these loop-shaped transmission paths. In the data transmission system, each of the plurality of data transmission devices is provided with a signal from the upstream side of the loop-shaped transmission line currently being used as an active system, and the signal is a failure pattern signal indicating a failure state. a detecting means for detecting whether or not there is a fault pattern; and when the detecting means detects the fault pattern signal, the fault pattern signal is sent downstream of the loop-shaped transmission line currently being used as an active system, and a fault state is detected. a signal generating means for transmitting a specific signal that does not indicate a failure pattern downstream of the loop-shaped transmission line currently being used as a standby system; a transmitting means; a receiving means; and after the detecting means detects the failure pattern signal. When the specific signal is detected from the loop-shaped transmission line currently used as a standby system within a predetermined time, the loop-shaped transmission line currently used as an active system is used as a standby system. and a transmission connection for connecting the transmitting means and the receiving means to the loop-shaped transmission line currently used as a standby system in order to use the loop-shaped transmission line currently used as a standby system as an active system. When the switching means and the detecting means do not detect the specific signal from the loop-shaped transmission line currently being used as a standby system within a predetermined time after detecting the failure pattern signal, the switching means and the detecting means detect the failure pattern signal and, when the specific signal is not detected from the loop-shaped transmission line that is currently being used as a standby system, a first operation of transmitting the specific signal to the loop-shaped transmission line currently being used as a system and connecting the transmitting means; and a first operation of transmitting the specific signal to the loop-shaped transmission line currently being used as the operational system; a second operation of connecting, and a third operation of transmitting the failure pattern signal via the transmitting means when the specific signal sent in the first operation does not return within a predetermined time. and loopback connection means for performing the loopback connection.

Principle and operation of the invention According to the present invention, a signal interruption (special pattern) is identified in the active system, a signal interruption is given to the active system, a signal that does not fail is sent to the standby system, and a signal that does not become interrupted is sent to the standby system for a certain period of time. By equipping each transmission device with a function that switches the system if it is flowing, and switches to a loopback state if it is not flowing, in the event that both the active and standby systems are disconnected in a certain section, It is possible to switch to a loopback state so that this section is not involved in signal transmission and continue signal transmission.

Embodiment of the Invention Next, an embodiment of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, the system to which the present invention is applied includes transmission devices 1 to 4, first loop transmission lines 11 to 14, and second loop transmission lines 2.
It consists of numbers 1 to 24. During normal system operation, the transmission lines of loop 0 systems 11 to 14 are used, and the transmission lines of loop 1 systems 21 to 24 are placed in a bypass state (described later). Referring to FIG. 2, one embodiment of the present invention includes a first photoelectric conversion circuit 3
0, second photoelectric conversion circuit 31, clock lines 51 and 6 for transmitting the clock signal after photoelectric conversion
1. Data line 5 that transmits data after photoelectric conversion
2 and 62, transmission line control circuit 32, clock lines 54 and 64 for transmitting clock signals to be sent to the loop system transmission lines 11 and 21, and clock lines 54 and 64 for transmitting data to be sent to the loop system transmission lines 11 and 12. Data lines 55 and 56, control signal lines 56 and 66 that transmit control signals for separately controlling the first and second photoelectric conversion circuits 30 and 31, a processor 33 that performs microprogram control, and a data bus 81. , an interrupt line 82, a signal line group 83 that transmits control signals for controlling the transmission line control circuit 32, and a data line 8 that transmits data to be sent to the loop system transmission line.
4. Data line group 8 that sends data received from the loop system transmission lines 22 and 14 to the processor 33
5. Transmits a transmission request signal that turns on when it is desired to send data given through the write pulse line 86 that transmits the write pulse and the data line 84 from the processor side 33 to the loop system transmission lines 11 and 21. It consists of a request signal line 87. Referring to FIG. 3, the transmission line control circuit 32 of FIG.
A clock signal disconnection detection circuit 91, a transmitting/receiving circuit 92 for transmitting and receiving data from or to the loop system transmission line, a flip-flop 101 indicating that transmission to the first loop system transmission line is possible, and a second loop system transmission line. Flip-flop 201 indicates that transmission is possible from the first loop transmission line, and flip-flop 10 indicates that reception from the first loop transmission path is possible.
2. Flip-flop 202 that indicates that reception from the second loop-based transmission line is possible; flip-flop 103 that issues a bypass instruction to the first loop-based transmission line; and flip-flop 103 that issues a bypass instruction to the second loop-based transmission line. 203, a signal line 301 that sends out a clock detection signal indicating the detection of an uninterrupted signal, an output signal line 321 that sends out the output signal of the flip-flop 102, an output signal line 322 that sends out the output signal of the flip-flop 202, and an AND circuit 401. It is configured. Fourth
Referring to the figure, the clock signal disconnection detection circuit 91 in FIG. A counter 111 is used to identify whether or not the logical value "1" continues until the input data of the system transmission line reaches the value of constant T0. The counter 112 continues counting until it reaches the value of constant T1 unless a value is detected, and the counter 112 continues counting until it reaches the value of constant T2 unless the logic value "0" of the input data of the loop system transmission line is detected when the connection state flip-flop 110 is on. A clock signal line 315 that provides an internal clock, a reset signal line 316 that provides a master reset signal, a signal line 317 that transmits a reset signal from the host device to reset the clock-off flip-flop 114, and a NAND circuit. 402, an OR circuit 403, and a receiver 411.

Next, the operation of one embodiment will be explained in detail. In the normal state, the first loop transmission lines 11 to 14 are used. Assume that the first loop transmission line is now used. The data transmission device 1 includes a transmittable flip-flop 101 for a first loop-based transmission line, a receive-capable flip-flop 102 for the first loop-based transmission line, and a bypass flip-flop 203 for the second loop-based transmission line. It is in the on state, and the output signal 301 of the clock signal disconnection detection circuit 91 is in the on state. In addition, other data transmission device 2 in FIG.
~4 is also in the same state as the transmission device 1,
Each of them is connected to a first loop system transmission line. Referring to FIG. 2, if the first loop transmission line 14 and the second loop transmission line 21 are simultaneously disconnected in this state, the first loop transmission line 21 of the first loop transmission line in the data transmission device 1 The photoelectric conversion circuit 30 sets the data line 52 to all1. In response to the signal applied via the data line 52, an interrupt signal is sent from the clock signal disconnection detection circuit 91 to the signal line 8.
2 is output. In response to the interrupt signal provided via signal line 82, processor 33 sends data and write pulses via data line 81 and write pulse signal line 86. In response to these data and write pulses, the respective states of the transmit enable flip-flop 101 and the receive enable flip-flop 102 for the first loop system transmission line are turned off, and the clock and data are transmitted to the first loop system transmission line. Make sure that the clock signal is not flowing (clock signal disconnected state). A state in which both the clock signal and data are not flowing is a state in which a failure pattern signal indicating a clock disconnection failure is flowing. At the same time, the transmittable flip-flop 201 for the second loop transmission line is turned on, and the bypass flip-flop 203 is turned off. At this time, since the transmission request signal line 87 is in the off state,
The transmitting/receiving circuit 92 can continuously send a pattern in which the clock signal is not interrupted to the loop transmission line. After a predetermined time has elapsed, the receivable flip-flop 202 for the second loop transmission line is turned on, and the processor 33 detects the signal on the clock detection signal line 301, which is the output of the clock signal disconnection detection circuit 91. However, since the loop transmission line 11 is in the same state as a disconnection, the data transmission device 2 also performs the same operation as the data transmission device 1 described above. Therefore, since the data transmission device 2 continuously sends out a pattern in which the clock signal is not cut off to the second loop transmission line 22, the transmission line 22 is not in a state where the clock signal is cut off.
As a result, when the processor 33 of the data transmission device 1 tries to detect the signal on the clock detection signal line 301, this signal is in the on state, so the processor 33 detects the signal on the clock detection signal line 301. By turning on the loop 103, the first loop system is switched to the second loop system. In this way, the clock signal disconnection is successively propagated to the data transmission device 4, and the transmission path is switched to the second loop system transmission line. The operation of the data transmission device 4 is such that the processor 33 of the data transmission device 4 detects the clock detection signal line 301 because the transmission line 21 is disconnected.
It is turned off when it detects a signal. Therefore, the receivable flip-flop 202 corresponding to the second loop system is turned off, and the receivable flip-flop 10 corresponding to the first loop system is turned off.
2 is turned on and the signal on the clock detection signal line 301 is detected. At this time, since the data transmission devices 1 to 3 corresponding to the first loop system are in a bypass state, the clock signal is cut off. Therefore, since the signal on the clock detection signal line 301 of the data transmission device 4 is off, the processor 33 turns off the transmittable flip-flop 201 for a certain period of time, and returns it to the on state after a certain period of time. That is, the data transmission device 4
becomes a loopback state in which the first loop system is on the receiving side and the second loop system is on the transmitting side, causing the clock signal to be interrupted on the transmission line 24 for a certain period of time. Then, the processor 33 of the data transmission device 3 detects the ON state of the interrupt signal line 82 when the clock signal is disconnected, and uses the data on the data line 81 and the pulse on the write pulse line 86 to enable transmission corresponding to the second loop system. Flip-flop 201 and receivable flip-flop 202
is turned off to prevent clocks and data from flowing through the second loop transmission line. Then the first
The transmittable flip-flop 101 corresponding to the loop system is turned on, and the bypass flip-flop 1 is turned on.
03 is turned off. At this time, since the transmission request signal line 87 is in the OFF state, the transmitting/receiving circuit 92 is configured to continuously send a pattern in which the clock signal is not interrupted to the first loop transmission line. After a predetermined period of time has elapsed, the contents of the receivable flip-flop corresponding to the first loop system are turned on;
The processor 33 goes to detect the signal on the clock detection signal line 301 which is the output of the clock signal disconnection detection circuit 91. However, since the loop system transmission line 23 is in the same state as a disconnection, the data transmission device 2
also performs the same operation as the data transmission device 3 described above.
That is, a pattern in which the clock signal is not interrupted is continuously sent to the first loop transmission line. Therefore, the loop transmission line 12 is not disconnected from the clock signal. Therefore, when the processor 33 of the data transmission device 3 goes to detect the signal on the clock detection signal line 301, it is in the on state, so the contents of the bypass flip-flop 203 corresponding to the second loop system are is turned on to switch from the second loop system to the first loop system. In this way the second
The clock signal disconnection is successively propagated to the data transmission device 1 on the loop system side of the first loop system, and the transmission line is switched to the first loop system transmission line. The data transmission device 1 performs the same operation up to the middle. That is, the transmitter/receiver circuit 92 continuously sends a pattern that does not result in clock interruption to the first loop system transmission line, and after a predetermined time has elapsed, turns on the contents of the receivable flip-flop corresponding to the first loop system. The operation is exactly the same up to the point where the processor 33 monitors the signal on the clock detection signal line 301. However, since the transmission line 14 is disconnected in the subsequent operation of the data transmission device 1, when the processor 33 of the data transmission device 1 goes to detect a signal on the clock detection signal line 301, it is in the off state. . Therefore, the receivable flip-flop 102 of the first loop system is turned off, and the receivable flip-flop 202 corresponding to the second loop system is turned on (at this time, the receivable flip-flop 102 of the first loop system is turned off).
01 is on, bypass flip-flop 10
3 is in the off state, the data transmission device is in a loopback state), the clock detection signal line 3
Go to detect the 01 signal. At this time, the first loop system of the data transmission devices 2 and 3 is in a connected state,
Since the second loop system is in the bypass state and the data transmission device 4 is in the loopback state, the pattern in which the clock signal sent to the first loop system side of the data transmission device 1 is not interrupted is continuous. The data flows in the order of transmission device 1 → 2 → 3 → 4 → 3 → 2 → 1. As a result, the signal on the clock detection signal line 301 of the data transmission device 1 is turned on. Therefore, the process ends in this state. That is, the data transmission device 1 enters a loopback state in which the second loop system is on the receiving side and the first loop system is on the transmitting side. FIG. 5 shows the final state when the loop transmission lines 14 and 21 are disconnected. Next, the clock signal disconnection detection circuit 91 will be explained in detail. Now, when the receivable flip-flop 102 is set, the signal line 321 is turned on, and the input data and input clock from the first opto-electric conversion circuit 30 are provided via the lines 52, 51, the receiver 411 and the NAND gate 402. Counter 1
11 works. The counter 111 continues counting in response to the logic value "1" of the input data from the opto-electrical conversion circuit 30, is reset in response to the logic value "0", and pulses in response to the counter value "T0". occurs. On the other hand, the counter 112
1 is on, but when the value of counter 111 becomes T0 or when connection state flip-flop 110 is set, counter 112 is reset. When the value of the counter 112 reaches "T1", a pulse is generated. Additionally, a connection state flip-flop 110 is set in response to the value "T1" of counter 112. Therefore, by turning on the clock detection signal line 301, which is the output of the flip-flop 110, the connection state of the loop system transmission line can be detected by the processor 3.
Let 3 know. Connection state flip-flop 110
is set and when the internal clock 315 is applied, the counter 113 counts if the input data is a logical value "1". The kakuunta 113 is reset in response to the logic value "0" of the input data. Eventually, in response to the value "T2" of the counter 113, the clock signal disconnection flip-flop 114 is set. Therefore, in response to the setting of the clock signal disconnection flip-flop 114, the interrupt signal line 82 is turned on. Therefore, the processor 33 is notified of the occurrence of the clock signal disconnection. Next, as a pattern in which the clock signal is not interrupted, a block diagram in which the number of consecutive logical values "1" is less than T0 is shown in FIG. 6, and will be described below. Reference numeral 511 is a clock signal line that provides a clock for transmission, reference numeral 501 is a counter, reference numeral 51
3 is a line that outputs 1 bit of the counter value,
Reference numeral 502 indicates a selector, and reference numeral 512 indicates a line that transmits a pattern in which the clock signal is not interrupted at the output of the selector. Now selector 50
2 is output signal line 5 in response to the value “0” on line 513.
12 and outputs '1' to the output signal line 512 in response to the count value '1' on the line 513. Therefore, the clock signal line 5 is connected to the counter 501.
If a clock signal is constantly applied through the clock signal 11, a continuous pattern can be generated repeatedly. In this case, the counter 501 is a circuit such that the number of "1"s in "111...1" is less than the constant T0. The operations of each data transmission device described above are shown in the flowchart of FIG. However, bypass is
Considering the photoelectric conversion circuit 30, when the bypass signal line 56 is on, the transmission clock line 54 and the transmission data line 55 are ignored, and the input signal of the photoelectric conversion circuit 30 goes out as an output signal in a loop. That's what it means. In the above example, the receive clock line 51 and the receive data line 52 are valid even during bypass.

Effects of the Invention The present invention is configured so that after a certain period of time after the active system is disconnected and the standby system is sent an unavoidable signal, the standby system enters a loopback state unless the signal is valid. This has the effect of automatically re-configuring the entire system.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a loop transmission system to which the present invention is applied, FIG. 2 is a diagram showing an embodiment of the present invention, and FIG. 3 is a diagram showing an example of the transmission line control circuit of FIG. 2. 4 is a diagram showing an example of the clock signal disconnection detection circuit shown in FIG. 3, FIG. 5 is a diagram showing a loop transmission system after implementing the present invention, and FIG. 6 is a portion of the transmitting/receiving circuit shown in FIG. 3. FIG. 7 and FIG. 7 are diagrams showing the operation of an embodiment of the present invention. 1 to 7, 1 to 4... data transmission device, 11 to 14, 21 to 24... transmission line,
30, 31...Photoelectric conversion circuit, 51, 52, 5
4-56, 61, 62, 64-66, 81-8
7,301,311,312,315-317,
321, 322, 511-513...Signal line, 3
2...Transmission path control circuit, 33...Processor, 9
1...Clock disconnection detection circuit, 92...Transmission/reception circuit, 101-103, 201-203, 110,
114...Flip-flop, 111-113,
501...Counter, 401-403...Gate, 411...Receiver, 502...Selector.

Claims (1)

[Claims] 1. A data system comprising two parallel loop-shaped transmission paths in which signals flow in directions opposite to each other, and a plurality of data transmission devices connected to both of these loop-shaped transmission paths. In the transmission system, each of the plurality of data transmission devices receives a signal from the upstream side of the loop-shaped transmission line currently being used as an active system, and determines whether the signal is a failure pattern signal indicating a failure state. detecting means for detecting whether or not the fault pattern signal is detected; a signal generating means for transmitting a specific signal to the downstream of the loop-shaped transmission line currently being used as a standby system; a transmitting means; a receiving means; If the specific signal is detected from the loop-shaped transmission line currently being used as a standby system within a time period, the loop-shaped transmission line currently being used as an active system is used as a standby system, and the transmission line connection switching for connecting the transmitting means and the receiving means to the loop-shaped transmission line currently being used as a standby system in order to use the loop-shaped transmission line currently being used as a standby system as an active system; means; when the detection means does not detect the specific signal from the loop-shaped transmission path currently being used as a standby system within a predetermined time after detecting the failure pattern signal, the detection means detects the failure pattern signal; a first operation of transmitting the specific signal and connecting the transmitting means to the loop-shaped transmission line currently being used as an active system; and connecting the receiving means to the loop-shaped transmission line currently being used as the active system. and a third operation of transmitting the failure pattern signal via the transmitting means if the specific signal transmitted in the first operation does not return within a predetermined time. What is claimed is: 1. A data transmission device comprising: loopback connection means for connecting