JPH0376089A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To read out data at a high speed in the case a write address and a read-out address approach each other by providing a static type data latch means for holding temporarily write data, and outputting this holding data to the outside in response to the approach of the write address and the read-out address. CONSTITUTION:The device is provided with static type data latch means 21, 22 for holding temporarily write data in parallel to data write to a dynamic type memory cell array 10, so that when a write address and a read-out address approach each other, this holding data is outputted to the outside instead of read-out data from the dynamic type memory cell array 10 or a read data register 2. That is, its data can be outputted to the outside without waiting for the end of a write cycle of data to the read-out address of the dynamic type memory cell array 10. In such a way, read-out of data in the case the write address and the read-out address of a first-in first-out format approach each other can be executed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a first-in, first-out (FIFO) type semiconductor memory device including a dynamic memory cell array, and a technique for speeding up read operations therein.
For example, the present invention relates to a technique that is effective when applied to a DRAM (random access memory) type input capacity FIFO buffer memory.

[Prior art]

FIFO buffer memories are widely used where data is exchanged between units with different data processing speeds. Here, in terms of system operating efficiency, such a FIF* buffer memory is desired to be able to be accessed at high speed and to have a large storage capacity. In this respect, SRAM (static random access memory) type FIFO, which has been provided conventionally,
Even if a buffer memory can be accessed at high speed, it is difficult to obtain a sufficiently satisfactory storage capacity because the number of transistors forming the memory cell is large. Therefore, it is being considered to configure a FIFO buffer memory using a RAM with a large storage capacity. For example, ESSCIRC1986De
rA Bidirecti announced at lft
onalData T, transmission
32KX8Dual Port FIFO Memo
-ry” (pages 47 and 48). This PIF
The O-buffer memory has a 256-bit dynamic memory cell array and a 64-byte read data register and a 64-byte write data register between this dynamic memory cell array and a human output buffer that is interfaced with the outside in bytes. It has registers, and 64 bytes of data are transferred to and from the respective data registers all at once to and from the memory cell array. As a result, ■ times of DRA
The number of data read and written by M memory cycles increases, which apparently increases the access speed and also increases the storage capacity.

[Problems to be Solved by the Invention] Due to the nature of FIF○ memory, write addresses and read addresses may be close to each other. For example, there is a case where a read operation is instructed at almost the same timing as a write operation after reset. In such a case, the conventional FIF
In O-buffer memory, data must be written to a dynamic memory cell array and then read from the memory cell array. Therefore, when the top address and the read address are close to each other, for example, a write instruction to the same address cannot be issued. When a read instruction is issued, it is necessary to wait for the memory cycle of the DRAM before reading the necessary data.

The inventor has revealed that there is a problem in that the data read speed is delayed.

Furthermore, in order to improve functionality, a retransmission mode may be added to the FIFO buffer memory. This retransmission mode is an operation mode for instructing to read data again from the first address during the operation after resetting the built-in address counter.

When this operation mode is set, the value of the read address counter is initialized to the first address, and data is sequentially read from the first address. Therefore, it is necessary to wait for the completion of the DRAM read cycle before the data at the first address is read out to the outside, and this also causes the problem that the data read speed is delayed as described above. revealed by the inventor.

An object of the present invention is to read data when a write address and a read address are close to each other in a first-in, first-out format.
An object of the present invention is to provide a semiconductor memory device that can perform high-speed access without waiting for a RAM access cycle.

Another object of the present invention is to
DRA mode for reading data from the first address
An object of the present invention is to provide a semiconductor memory device that can perform high-speed access without waiting for M access cycles.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, FI including a dynamic memory cell array
In an FO type semiconductor memory device, a static type data latch means is provided to temporarily hold the written data in parallel with data writing to the dynamic type memory cell array, and the internally generated write address and read address are close to each other. Correspondingly, the data held by the static data latch means is outputted to the outside instead of the data read from the dynamic memory cell array.

When inputting and outputting data to a dynamic memory cell array via a write data register/read data register, the output data of the read data register is changed in response to the proximity of the internally generated write address and read address. Instead, the data held by the static data latch means is output.

Here, the proximity of the write address and the read address can be defined as the difference between the write address and the read address to the dynamic memory cell array being equal to or less than the number of data held by the static data latch means.

In addition, in a FIF○ format semiconductor memory device that includes a dynamic memory cell array and inputs and outputs data to the dynamic memory cell array via a write data register/read data register, data is stored at the first address of the dynamic memory cell array. When a write is performed, a start address data holding means is provided to statically hold the write data at the start address in parallel with this, and in order to instruct reading of data again from the start address in the middle of the operation after reset. In response to the designation of the retransmission mode, the first address is read from the first address data holding means, and in parallel with this operation, data is transferred from the second access address of the memory cell array to the read data register. This is to read out the .

[For production]

According to the above means, when the write address and the read address are close to each other, the data held in the static data latch means is outputted to the outside instead of the read data from the dynamic memory cell array or the read data register. It is possible to output the data at the read address to the outside without waiting for the end of the data write cycle for the read address in the memory cell array. D.R.
To achieve high-speed access without waiting for an AM access cycle.

The conditions for reading data from the static data latch means, that is, the proximity of the write address and the read address, are determined by the cycle time of writing and reading from the dynamic memory cell array and outputting the read data to the outside. The static data latch means is set to have a storage capacity that can hold all the write data supplied from the outside during the series of cycles, and
By defining the proximity state between the write address and the read address as the difference between the write address and the read address to the dynamic memory cell array being equal to or less than the number of data held by the static data latch means,
6. Also, the output selection control of the static data latch means is simplified. When the transmission mode is specified, the first address is read from the first address data holding means, and during that time the second address of the memory cell array is read.
Performing the data read operation from the first access address makes it possible to output the data at the first address to the outside without waiting for the end of the read cycle for the first address of the dynamic memory cell array. Following the data output of , the data of subsequent access addresses can also be output continuously, thereby allowing data to be read from the first address in transmission mode at high speed without waiting for the access cycle of the DRAM. Achieve.

〔Example〕

FIG. 1 shows a FIFO buffer memory according to an embodiment of the present invention. The FIFO buffer memory shown in the figure is formed on a single semiconductor substrate such as silicon by a known semiconductor integrated circuit manufacturing technique, although this is not particularly limited. The FIFO buffer memory of this embodiment is configured to serially input and output data to and from the outside, although this is not particularly limited.

This FIF○ buffer memory has DRAM section 1 inside 71
．． Read data input/output to the DRAM section using data register 2. The write data is performed via the write data register 3, and an address counter unit 5 that generates an access address for the DRAM module. DRA readout
An additional circuit section 6 for speeding up data reading from the first address in the transmission mode without waiting for the access cycle of the DRAM section 1, and the overall system. The controller 7 includes a controller 7 that controls timing and operation mode.

The DRAM section 1 includes a memory cell array 10 in which dynamic memory cells (not shown) are arranged in a matrix.Selection terminals of memory cells (not shown) are driven to a selection level row by row, that is, word line by word line, by the output of a row address decoder 11. . Complementary bit lines to which data input/output terminals of memory cells are coupled for each column are connected to the column selection switch circuit 12 on one side, and to a precharge circuit and a sense amplifier (not shown) on the other side. The column selection switch circuit 12 selects, for example, three complementary bit lines selected by the output of the column address decoder 13.
It is selected in units of 2 bits and connected to the input terminal of the read data register 2 via the read common data line 14 and to the output terminal of the write data register 3 via the aligned write common data AID5.

The read data register 2 is a 32-bit parallel-in/serial-out type register, and each bit is constituted by a static latch circuit (not shown). Also, write data register 3 is a serial input.
It is a 32-bit parallel-out register, and each bit is configured by a static latch circuit (not shown).

The address counter section 5 includes a write address counter 17, a read address counter 18, and a refresh address counter 19. Write address counter 17
is an i-bit block write address Abw for specifying the row address and column address of the memory cell array 10.
and a 5-bit serial write address ASW that sequentially specifies the 32 input bits in the write data register 3, and is constituted by an i+5-bit binary counter. The 5-bit serial write address A sw is assigned to the lower 5 bits, and the block write address Abw is assigned to its upper bits. The read address counter 18 performs a 5-bit serial read function that sequentially specifies the i-bit block read address Abr for specifying the row address and column address of the memory cell array 10 and the 32-bit output bit in the read data register 2. It outputs the address Asr, i+5
Consists of a binary counter of bits. In addition, 5
The bit serial read address Asr is assigned to the lower 5 bits, and the block read address Abr is assigned to its upper bits. The refresh address counter 19 generates a refresh address Aref corresponding to the row address.

The block read address Abr, block write address Abw, and refresh address Aref are supplied to an address selection circuit 20, and a predetermined address is selected according to the internal operation mode and supplied to the row address decoder 11 and column address decoder 13. For example, when a refresh operation is instructed by the controller 7, the refresh address Aref is selected and supplied to the row address decoder 11. As a result, the data held in the memory cells connected to the word line selected by the refresh address Aref is refreshed. When a write operation to a memory cell is instructed by the controller 7, a block write address Abw is selected and taken in, and a word line is first selected according to the row address included in the address Abw, and the word line is selected. A bit line is selected by the column address at the timing when the line selection state is determined, and data is thereby written into the memory cell corresponding to 32 bits specified by the block write address Abw. When a read operation of a memory cell is instructed by the controller 7, a block read address Abr is selected and taken in, and a word line is first selected according to the row address included in the address Abr, and the word line is selected. A bit line is selected by the column address at the timing when the line selection state is determined, and data is thereby read from the memory cell corresponding to 32 bits specified by the block read address Abr.

The additional circuit section 6 has a first data register 21 that temporarily holds the data in parallel with data input to the write data register 3, and when data is written to the first address of the memory cell array 10, In parallel with this, it includes a second data register 22 that holds the write data at the start address, and the first data register 21, the second
The respective outputs of the data register 22 and the read data register 2 are given to an output selection circuit 23, and the output selection circuit 23 selects one of them and outputs it to the outside.

Although the first data register 21 is not particularly limited,
It has a serial-in/serial-out format including a 64-bit state latch circuit, and the input bit address is specified by the write address pointer 25, and the output bit address is specified by the read address pointer 26.

The write address pointer 25 is supplied with the output address of the lower 6 bits of the write address counter 17, that is, the least significant bit of the serial write address Asw and the block write address Abw, and is supplied with the latest write data bit input to the write data register 3. Up to 64 bits of past data is stored sequentially based on the . The read address pointer 26 is supplied with the lower 6 bits of the output address of the read address counter 18, that is, the least significant bits of the serial read address Asr and the block read address Abr. The written bits are serially output in sequence.

Although the second data register 22 is not particularly limited,
It has a serial-in/serial-out format including a 32-bit state latch circuit, and the input bit address is specified by the write address pointer 30, and the output bit address is specified by the read address pointer 31.

The write address pointer 30 is supplied with the serial write address Asw output from the write address counter 17, and this serial write address Asw
The input bit address designation operation is performed by the address decoder 32 that decodes the block write address Abw.
is enabled when the first address in the memory cell array 10 is detected. Therefore, the second data register 2
2 holds 32-bit data to be written to the first address of the memory cell array 10. The read address pointer 31 contains the read address counter 1.
The serial read address Asr output from the read data register 2 is supplied, and the head address data is serially outputted in synchronization with the serial output to the read data register 2.

The output selection circuit 23 is configured to
The output of the second data register 22 is selected by the control signal φrs that is asserted in synchronization with the output timing of the first access address when setting the mode, and the output of the second data register 22 is selected according to the proximity of the internally generated write address and read address. The output of the first data register 21 is selected by the asserted control signal φnear, and the output of the read data register 2 is selected in other data output operations.

Detection of proximity between the write address and the read address is performed by a subtracter 35 and a decoder 36, and the decoder 36 generates the control signal φnear. The subtracter 35 calculates the difference between the i+5-bit write address (block write address A b w and serial write address A'sW) output from the write address counter 17 and the read address (block read address Abr and serial read address Asr). The decoder 36 decodes the result of the operation, and asserts the control signal φn8ar when there is a difference of two or less addresses in the block address.

The above-mentioned transmission transmission mode is an operation mode that instructs to read data again from the first address during the operation after reset, and the transmission signal RT is asserted to low level. It is set by When the operation mode is set, the value of the read address counter 18 is forced to the address next to the first address, and data read operation from the memory cell array 10 at the address is enabled.
During the first DRAM read cycle, the head address data in the first memory cell array 10 is outputted from the second data register 22 to the outside by the control signal φrt, using a period until the memory cell data is still available in the read data register 2. It is now possible to do so.

The controller 7 receives a beam/transmission signal R.
In addition to T, reset signal RESET, write clock WC
LK and read clock RCLK are supplied. When the reset signal RESET is asserted, the values of the write address counter 17 and the read address counter 18 are initialized to the leading address and cleared.

The write clock WCLK is regarded as an external signal for defining the input timing of serial data in various registers, the increment timing of the write address counter 17, and the write timing for the memory cell array 10. That is, when the write clock WCLK is changed, the write address counter 17 is controlled by the control lock φWC that is synchronized with the change in the clock.
are sequentially incremented, and accordingly, the serial block write address A b w is incremented in the 32nd cycle of the write clock WCLK, and the serial write address A s is incremented in synchronization with each clock cycle.
w is changed cyclically.

Furthermore, in synchronization with the timing in which the block write address Abw is incremented once every 32 cycles of the write clock WCLK, a write operation to the memory cell array 10 is instructed by the block write address Abw immediately before such increment. Furthermore, memory cell array 1
When 0 is in the full state, changes in the write clock WCLK are ignored within the controller 7.

The read clock RCLK is regarded as a control signal for defining the output timing of serial data in various registers, the increment timing of the read address counter 18, and further the read cycle timing for the memory cell array 10. That is, when the read clock RCLK changes, the read address counter 8 is sequentially incremented by the control clock φrC synchronized with the change in the clock, and the block read address Abr is incremented once every 32 cycles of the read clock RCLK. With,
Serial read address Asr is cyclically changed in synchronization with each clock cycle. Further, data read operation for the memory cell array 10 is instructed by the block read address Abr in synchronization with the timing at which the block read address AbW is incremented in the 32nd cycle of the read clock RCLK.

Note that when the read clock RCLK is first continuously changed after reset and a read operation for the memory cell array 10 is performed, the controller 7 uses the read clock R
Read address counter 1 after CLK stops changing
The block read address Abr of 8 is incremented by 1, and the memory cell array 10 is read accessed using the incremented address, and the read data is internally transferred to the read data register 2 in advance. Therefore, the next time the read clock RCLK is changed, data is serially output from the read data register 2 in synchronization with the change, and when the read clock RCLK is changed by 32 clock cycles, the next serial readout starts. In preparation, a DRAM read cycle is performed using the next block write address, and the read data is latched into the read data register 2.

Next, an example of the operation of the FIF○ buffer memory of this embodiment will be described with reference to the timing chart shown in FIG.

When the reset signal RESET is asserted at time t0 and the read address counter 18 and write address counter 17 are reset, both address counters 17
．． The output address No. 18 is initialized to the first address. That is, the block write address Abw output by the write address counter 17 is initialized to address #O, the serial write address 1 address is initialized to address $O, and the block read address Abw output by the read address counter 18 is initialized to address #O.
is initialized to address #0, and the serial read address is initialized to address $O.

When the write clock WCLK is sequentially changed by 32×7 cycles from time t1, the input data Din sequentially applied from the outside is serially input to the write data register 3 in synchronization with the clock change, and the 32×7 cycles of the write clock WCLK are A write cycle of the DRAM section 1 is activated every time the clock changes, and data in the write data register 3 is written to the memory cell array 10 in units of 32 bits. In this write operation, input data Din is sequentially stored in the first data register 21 in synchronization with changes in the write clock WCLK. In addition, in such a write operation, when the write clock WCLK is changed by 32 clocks for the first time, the block write address Abw points to address #0 as the first address. The pointer 3o is controlled to be operable,
As a result, the same 32-bit data as the data to be written to address #O of the memory cell array 10 is held in the second data register 22.

In FIG. 2, the read clock RCLK is sequentially changed by 32×3 cycles from time t2 immediately after time t. Data is serially output from the first data register 21 and the second data register 22 in synchronization with the clock change of the read clock RCLK. At this time,
Read address counter 1 is synchronized with the clock change.
8 is incremented, and in this state, the subtracter 3 subtracts the output address of the read address counter 18 from the output address of the write address counter 17.
Since the value of 5 is a block address with a difference of less than 2 addresses, in other words, the write address and read address are close, so the output selection circuit 23 uses the control signal φn88.
The output of the first data register 21 is selected by r.

Therefore, as long as the write address and the read address are close to each other, the write data once taken into the first data register 21 is serially output to the outside as output data DOUT. That is, data at a desired address can be read externally at high speed without waiting for a DRAM cycle from when data is written to addresses #0, #1, and #2 in the memory cell array 10 until it is read.

When the data output operation from the first data register 21 is performed in this manner, the increment operation of the read address counter 18 and the data read operation from the memory cell array IO to the read data register 2 are performed according to the normal procedure. In particular, such a memory cell array 1
Since the read operation for 0 is the first read operation after reset, the controller 7 increments the block read address Abr of the read address counter 18 by 1 after the read clock RCLK stops changing after the read clock RCLK has stopped changing. At the same time, the memory cell array 10 is read accessed using the incremented address, and the read data is internally transferred to the read data register 2 in advance.

Due to this read cycle R3, the data at block read address #3 has already been internally transferred to the read data register 2. Therefore, when the read clock RCLK is changed again at time t, the data at block read address #3 is output from the read data register 2 to the outside through the output selection circuit 23 in synchronization with the clock cycle.

Starting from the time t, or when the clock change of one clock RCLK is repeated 32 times, the value of the read address counter 18 is updated in synchronization with this, and the read cycle R4 for the memory cell array 10 is started. Become.

In this embodiment, the retransmission mode is set by the transmission signal RT at time t4 before the start of the read cycle R4. When such an operating mode is set, read address counter 1
A value of 8 is forced to address #1, and the read cycle R4
Then, a read operation for the memory cell array 10 is performed using address #1. In parallel with this read operation, the controller 7 asserts the control signal φrt to read #0 stored in the second data register 22.
The address data is read by the read clock R starting from time 1S.
The output selection circuit 23 outputs the signal to the outside in synchronization with the change in CLK. Subsequently, when the read clock RCLK is further changed for 32 cycles, the data at address #1 read out to the read data register 2 in read cycle R4 is outputted to the outside in synchronization with the clock RCLK. Ru. Therefore, after setting the transmission mode, the data at address #O is transferred to the memory cell array 10.
In other words, data at the first address can be immediately read externally without performing a DRAM cycle to read from the memory, or without waiting for the completion of the RAM read cycle, and data at subsequent addresses can also be read continuously. become.

According to the above embodiment, there are the following effects. 9 (1) In parallel with data writing to the memory cell array 10, the first data register 21 that temporarily holds the written data is provided, and the internally generated writing As the address approaches the read address, the data held in the first data register 21 is outputted to the outside instead of the read data of the memory cell array 10, that is, the output data of the read data register 2. The data at the read address can be immediately output to the outside without waiting for the completion of the DRAM write cycle and read cycle.
This allows the DRA to read data when the write address and read address are close to each other in the first-in, first-out format.
This can be done at high speed without waiting for M access cycles.

(2) The condition for reading data from the first data register 21, that is, the proximity state between the write address and the read address, is a series of cycles leading to writing and reading from the memory cell array 10 and external output of the read data. Determined in relation to time. At this time, the first data register 21 is set to have a storage capacity capable of holding all the write data supplied from the outside during the series of maximum cycle periods, that is, a storage capacity of 64 bits, and The state of proximity between the write address and the read address is defined as the difference between the write address and the read address to the memory cell array 10 being equal to or less than the number of bits of the storage capacity of the first data register 21 or equal to or less than two addresses in block address units. Therefore, the output selection of the first data register 21 can be controlled relatively easily or simply.

(3) When data is written to the start address of the memory cell array 10, that is, block address #0, a second data register 22 is provided to statically hold the write data at the start address in parallel. In response to the designation of the transmission mode, the first address is read from the second data register 22, and in parallel with this operation, the DRAM is read from the second access address of the memory cell array 10, that is, the block address #1. Since the read cycle is started, the data at the first address can be output to the outside without waiting for the end of the read cycle for the first address of the memory cell array 10, and following the output of the data at the first address, the data at subsequent access addresses can be output. Data output can also be performed continuously.

Therefore, data can be read from the first address in the transmission mode at high speed without waiting for a DRAM access cycle.

Although the present invention has been specifically described above based on examples, the present invention is not limited thereto, and can be modified in various ways without departing from the gist thereof.

For example, in the above embodiment, a case has been described in which data is exchanged with the outside through l serial input terminals and l serial output terminals, but parallel serial input/output may be performed by increasing the number of serial input/output terminals. It can also be configured as follows. In this case, the additional circuit section 6 may be provided for each of the serial input/output systems, but the subtracter 35, decoder 36, address decoder 32, etc. can be shared. Furthermore, the unit of data that is input and output bit serially is not limited to 32 bits, but can be changed as appropriate.

Further, in the above embodiment, a configuration was described in which data is serially input/output using a read data register 2 and a write data register 3. However, the present invention is not limited thereto, and is not limited to a DRAM that inputs/outputs data in parallel.
It can also be applied to type FIFO buffer memory,
In that case, it is not necessary to use the data registers 2 and 3 that function as shift registers.

Furthermore, the configuration for high-speed access when the write address and read address are close together, as explained in the above embodiment, and the configuration for high-speed access when setting the transmission mode do not necessarily have to be both adopted. ,
Only one of the configurations may be used.

In the above description, the invention made by the present inventor was mainly applied to a FIFO buffer memory single chip, which is the field of application that formed the background of the invention, but the present invention is not limited thereto, and is applicable to microcomputer LSI
It can also be applied by being built into a communication LSI.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, in parallel with data writing to the dynamic memory cell array, a static data latch means for temporarily holding the written data is provided, and in response to the proximity of the internally generated write address and read address, the memory Since the data held in the static data latch means is outputted to the outside instead of the data read from the cell array, data can be read without waiting for the access cycle of the DRAM when the write address and read address in the first-in, first-out format are close to each other. This has the advantage that it can be performed at high speed.

Further, the condition for reading data from the static data latch means, that is, the proximity state between the write address and the read address, is a series of cycles leading to writing and reading from the dynamic memory cell array and external output of the read data. Although determined in relation to time, the static data latch means is set with a storage capacity capable of holding all write data supplied from the outside during the series of maximum cycle periods, and , since the proximity state between the write address and the read address is defined in the detection means as the difference between the write address and the read address to the dynamic memory cell array is equal to or less than the number of data held by the static data latch means; This has the effect that the output selection of the static data latch means can be controlled relatively easily or simply.

Further, when data is written to the first address of the dynamic memory cell array, a first address data holding means is provided for statically holding the write data of the first address in parallel.

・In response to the transmission mode designation, reading of the first address is performed from the first address data holding means, and in parallel with this operation, a DRAM read cycle for the second access address of the memory cell array is started. This makes it possible to output the data at the first address to the outside without waiting for the end of the read cycle for the first address of the memory cell array, and also to output data at subsequent access addresses continuously after outputting the data at the first address. This has the effect that data can be read from the first address in the transmission mode at high speed without waiting for the access cycle of the DRAM.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a FIFO buffer memory according to an embodiment of the present invention, and FIG. 2 is an example operation timing chart of the FIFO buffer memory. 1...DRAM section, 2...Read data register. 3... Write data register, 5... Address counter section, 6... Additional circuit section, 7... Controller,
10...Memory cell array, 17...Write address counter, 18...Read address counter, 21
...First data register, 22...Second data register, 23...Output selection circuit, 32...Address decoder, 35...Subtractor, 36...Decoder, RT
...Transmission signal, WCLK...Write clock, RCLK...Read clock, Abr
...Block read address, Asr...Serial read address. Abw...Block write address, Asw...Serial write address 6

Claims (1)

[Claims] 1. A semiconductor memory device that includes a write address counter and a read address counter for generating access addresses for a dynamic memory cell array, and stores data in a first-in, first-out format according to the output address of the address counter, static type data latch means for temporarily holding written data in parallel with data writing to the dynamic type memory cell array; and static type data latch means for temporarily holding the written data in parallel with data writing to the dynamic type memory cell array; a selection means for outputting data held by the static data latch means to the outside in place of read data from the semiconductor memory device. 2. A dynamic memory cell array; a write address counter and a read address counter that generate access addresses for inputting and outputting data to the dynamic memory cell array in a first-in, first-out format; a write data register that supplies data to the dynamic memory cell array; a read data register that temporarily holds data read from the dynamic memory cell array and supplies it to the outside; and a write data register that supplies the write data to the write data register in parallel with When the access addresses held by the write address counter and the read address counter are close to each other, the data held by the static data latch means is output to the outside instead of the output data of the read data register. A semiconductor memory device comprising: selection means for selecting 3. Detecting proximity of the access addresses held by the write address counter and the read address counter when the difference between the read address and the write address to the dynamic memory cell array becomes equal to or less than the number of data held by the static data latch means. 3. The semiconductor memory device according to claim 1, further comprising a detection means. 4. a dynamic memory cell array; a write address counter and a read address counter that generate access addresses for accessing the dynamic memory cell array in a first-in, first-out format; a write data register that is applied to the dynamic memory cell array; a read data register that temporarily holds data read from the dynamic memory cell array and provides it to the outside; A start address data holding means that statically holds the write data at the start address in parallel with the above, and a retransmission mode for instructing to read data again from the start address in the middle of the operation after resetting the built-in address counter. In response to the designation, the first address is read from the first address data holding means, and in parallel with this operation, data is read from the second access address of the dynamic memory cell array to the read data register. A semiconductor storage device comprising: a control means;