JPH0376145A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0376145A
JPH0376145A JP21125489A JP21125489A JPH0376145A JP H0376145 A JPH0376145 A JP H0376145A JP 21125489 A JP21125489 A JP 21125489A JP 21125489 A JP21125489 A JP 21125489A JP H0376145 A JPH0376145 A JP H0376145A
Authority
JP
Japan
Prior art keywords
wiring
lower wiring
hole
layer wiring
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21125489A
Other languages
Japanese (ja)
Inventor
Yoshiaki Furukawa
古川 芳明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP21125489A priority Critical patent/JPH0376145A/en
Publication of JPH0376145A publication Critical patent/JPH0376145A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To improve the efficiency of treatment by performing surface treatment so that a lower wiring surface in a through hole which is formed at an organic resin film is treated with a dry etching process by the use of ozone and its lower wiring is treated with a wet etching process by the use of an etchant, and forming an upper wiring layer through a vacuum drying process. CONSTITUTION:Various thermal processes allow a wafer 6 to have a lower wiring oxide layer 4 on the surface of a lower wiring 5 consisting of Al. In such a case, for example, a polyimide like organic resin film 3 is applied to the wafer by rotation and it performs thermal setting. Then, its film 3 is treated with a wet etching process by the use of an etchant through a lithographic process by the use of a photoresist. Then, a through hole 1 is formed by peeling off the resist and an organic film 2 is formed on the lower wiring oxidizing layer 4 at the through hole part 1. Further, the surface treatment of the organic resin film 3 is performed with ozone 7 and irradiation of ultraviolet rays and then, the organic film 2 is removed. Then, surface treatment is performed with the etchant of Al and the above layer 4 is removed. Further, after performing vacuum drying treatment, the surface of lower wiring 5 at the through hole 1 is dehydrated while keeping the surface of its lower wiring layer clean. Then an upper wiring layer 9 is formed on the clean wiring layer 5.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は高細密化に対応する多層配線構造の半導体装置
の製造方法に関し、とくに配線の接続抵抗を低くするた
めに半導体装置の金属配線を表面処理する方法に関する
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device with a multilayer wiring structure that is compatible with high-density technology, and in particular, to a method for manufacturing a semiconductor device with a multilayer wiring structure that corresponds to high density. Concerning a method of surface treatment.

〔従来の技術〕[Conventional technology]

近年の半導体装置の高細密化への要求を満足するために
多層配線構造をとることは有効な方法であり、層間絶縁
膜として有機系樹脂膜は多用されてきている。
In order to satisfy the recent demand for higher densification of semiconductor devices, adopting a multilayer wiring structure is an effective method, and organic resin films have been frequently used as interlayer insulating films.

有機系樹脂膜を用いて多層配線構造にするとスルーホー
ルの上層配線と下層配線との接続部で抵抗を持ってしま
うことが知られている。スルーホール径が小さくなるほ
ど抵抗は大きくなり、スルーホール径104m以下では
半導体装置が正常に動作し々い位の高抵抗を持ってしま
う。この原因はスルーホール部の下層配線表面が薄い有
機系被膜で覆われてしまったり、種々の熱工程を経るた
めに酸化されるなどして、下層配線表面に絶縁性被膜が
形成されてしまうためである。
It is known that when a multilayer wiring structure is formed using an organic resin film, resistance occurs at the connection portion between the upper layer wiring and the lower layer wiring of the through hole. The smaller the diameter of the through hole, the greater the resistance, and if the diameter of the through hole is less than 104 m, the semiconductor device will have a high resistance that is too high for normal operation. The cause of this is that the surface of the lower layer wiring in the through-hole area is covered with a thin organic film, or that an insulating film is formed on the surface of the lower layer wiring due to oxidation due to various thermal processes. It is.

従来、絶縁性被膜の除去にはスパッタエツチング(また
はスパッタクリーニング)法が一般的に用いられている
。第2図(a)、(b)、(C)はスパッタエツチング
の様子を表した断面図である。
Conventionally, a sputter etching (or sputter cleaning) method has generally been used to remove the insulating film. FIGS. 2(a), 2(b), and 2(c) are cross-sectional views showing the state of sputter etching.

第2図(a)に示すようにAr(アルゴン)原子10が
活性化され、この活性化されたAr原子10が有機系樹
脂膜3とスルーホール1内の有機系被膜2に衝突する。
As shown in FIG. 2(a), Ar (argon) atoms 10 are activated, and the activated Ar atoms 10 collide with the organic resin film 3 and the organic coating 2 within the through hole 1. As shown in FIG.

Ar原子10の衝突により有機系被膜2表面を下層配線
酸化層4まで物理的に削り取っていき、スルーホール1
部の下層配線5表面の清浄な面を第2図(blに示すよ
うに出す。
The surface of the organic coating 2 is physically scraped down to the lower wiring oxide layer 4 by the collision of Ar atoms 10, and the through hole 1 is
The clean surface of the lower layer wiring 5 is exposed as shown in FIG. 2 (bl).

その後第2図(clに示すように上層配線9を形成し下
層配線5との導通をとる。
Thereafter, as shown in FIG. 2 (cl), an upper layer wiring 9 is formed and electrically connected to the lower layer wiring 5.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

スパッタエツチングによって表面処理を行う方法は、真
空装置を用いなげればならず大きな設備と投資が必要で
あり、Arによって削り取られた有機系樹脂によって装
置内が汚染されたり、真空引きに時間がかかりバッチ処
理であるので装置によって処理能力が制限されてしまい
処理効率がよくないなどの課題を有する。また、真空系
のメンテナンスも容易ではない。
The method of surface treatment by sputter etching requires the use of vacuum equipment and requires large equipment and investment, and the inside of the equipment may be contaminated by the organic resin scraped off by Ar, and it takes a long time to vacuum. Since it is a batch process, the processing capacity is limited by the equipment, resulting in problems such as poor processing efficiency. Furthermore, maintenance of the vacuum system is not easy.

本発明の目的は上記のような課題に着目し、近年の半導
体装置の高細密化を満足する多層配線構造をとる時に、
上層配線と下層配線を低抵抗で接続し大きな設備が不用
で処理効率のよい半導体装置の金属配線を表面処理する
方法を提供することにある。
The purpose of the present invention is to address the above-mentioned problems, and to provide a multilayer interconnection structure that satisfies the recent trend toward higher densification of semiconductor devices.
It is an object of the present invention to provide a method for surface treating metal wiring of a semiconductor device, which connects upper layer wiring and lower layer wiring with low resistance, does not require large equipment, and has high processing efficiency.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するため本発明の半導体装置の製造方法
においては、下記記載の方法により製造する。
In order to achieve the above object, a semiconductor device manufacturing method of the present invention is manufactured by the method described below.

下層配線上に層間絶縁膜として絶縁性を有する有機系樹
脂膜を形成し、有機系樹脂膜にスルーホールを形成後上
層配線を形成する半導体装置の製造方法において、有機
系樹脂膜に形成するスルー1ホール内の下層配線表面を
オゾンによる乾式エツチングと下層配線のエツチング液
による湿式エツチングにて表面処理し、その後真空乾燥
の工程を経て上層配線を形成することによって上記目的
を達成する。
In a semiconductor device manufacturing method in which an organic resin film having insulating properties is formed as an interlayer insulating film on a lower layer wiring, and a through hole is formed in the organic resin film, an upper layer wiring is formed. The above object is achieved by treating the surface of the lower layer wiring in one hole by dry etching with ozone and wet etching with an etching solution for the lower layer wiring, and then forming the upper layer wiring through a vacuum drying process.

〔作用〕[Effect]

有機系樹脂膜のスルーホール内の絶縁性被膜である有機
系被膜はオゾンにさらすことによって除去できる。下層
配線酸化層はその配線材料用のエツチング液を用いて表
面処理を行うことによってスルーホール部の下層配線表
面は清浄となる。その後真空乾燥で下層配線表面を清浄
に保ったまま吸着水分を除去して上層配線を形成するこ
とによって、上層配線と下層配線との低抵抗での接続が
可能となる。
The organic coating, which is an insulating coating inside the through-hole of the organic resin film, can be removed by exposing it to ozone. The lower wiring oxide layer is surface-treated using an etching solution for the wiring material, so that the surface of the lower wiring at the through-hole portion becomes clean. Thereafter, by vacuum drying to remove adsorbed moisture while keeping the lower layer wiring surface clean and forming an upper layer wiring, it becomes possible to connect the upper layer wiring and the lower layer wiring with low resistance.

表面処理にオゾンとエツチング液を用いることによって
スパッタエツチング装置のよう紅大きな設備は必要なく
、真空引きの必要も々いことから連続の処理が可能とな
り処理効率が向上する。
By using ozone and an etching solution for surface treatment, there is no need for large equipment such as a sputter etching device, and since there is no need for vacuuming, continuous treatment is possible and treatment efficiency is improved.

〔実施例〕〔Example〕

以下本発明の実施例を図面に基づいて詳述する。 Embodiments of the present invention will be described in detail below based on the drawings.

第1図(al〜(d)は本発明の表面処理方法を用いて
絶縁性被膜である有機系被膜2と下層配線酸化層4の除
去から上層配線9を形成するまでの工程を示した断面図
である。
FIGS. 1A to 1D are cross sections showing the steps from removing the organic film 2, which is an insulating film, and the lower wiring oxide layer 4 to forming the upper wiring 9 using the surface treatment method of the present invention. It is a diagram.

第1図(alに示すように、種々の熱工程により表面に
下層配線酸化層4を有しA3(アルミ−ニウム)から成
る下層配線5を形成したウェハー6に、例えばポリイミ
ドのような有機系樹脂膜6を回転塗布し熱硬化する。有
機系樹脂膜3は通常0,8μm〜3、Oμm程度の厚さ
に形成し、250°C〜400℃の温度にて30分〜9
0分間の熱硬化を行う。次にフォトレジストを用いるフ
ォトリングラフィ工程を経て有機系樹脂膜3を下記記載
の方法によりエツチングする。有機系樹脂膜3のエツチ
ングはヒドラジンとエチレンジアミンの混合溶液を用い
たエツチング液による湿式エツチング法、あるいはRI
 E (1(eactive Ion Etching
)による乾式エツチング液で行える。
As shown in FIG. 1 (al), a wafer 6 having a lower wiring oxide layer 4 on the surface and a lower wiring 5 made of A3 (aluminum) formed by various thermal processes is coated with an organic material such as polyimide. The resin film 6 is spin-coated and thermally cured.The organic resin film 3 is usually formed to a thickness of about 0.8 μm to 3.0 μm, and is heated at a temperature of 250° C. to 400° C. for 30 minutes to 90° C.
Perform heat curing for 0 minutes. Next, through a photolithography process using a photoresist, the organic resin film 3 is etched by the method described below. The organic resin film 3 can be etched using a wet etching method using an etching solution using a mixed solution of hydrazine and ethylenediamine, or by RI.
E (1(active ion etching)
) with a dry etching solution.

次にレジスト剥離を行ってスルーホール1を形成する。Next, the resist is removed to form through holes 1.

スルーホール1部の下層配線酸化層4上に有機系被膜2
が形成される。この有機系被膜2ができてしまう原因は
有機系樹脂膜3の形成やレジスト剥離リ等の工程によっ
て有機物が付着してしまうためである。
An organic film 2 is formed on the lower wiring oxide layer 4 of the through hole 1.
is formed. The reason why this organic film 2 is formed is that organic substances are attached during processes such as forming the organic resin film 3 and removing the resist.

次に第1図(b)に示すように、有機系樹脂膜30表面
処理をオゾン7と紫外線照射によって行い有機系被膜2
を除去する。表面処理の条件は有機系被膜2がごく薄い
ので比較的に軽く、酸素流量が1〜101/rtixの
場合、基板加熱温度が室温〜・3006Cの範囲で、時
間は1分〜30分間行う。
Next, as shown in FIG. 1(b), the surface of the organic resin film 30 is treated by ozone 7 and ultraviolet irradiation to form the organic resin film 2.
remove. The surface treatment conditions are relatively light since the organic film 2 is very thin, and when the oxygen flow rate is 1 to 101/rtix, the substrate heating temperature is in the range of room temperature to .3006C, and the time is 1 minute to 30 minutes.

紫外線照射をせずにオゾン7のみで表面処理をすること
も可能である。オゾン7には有機物を分解除去する作用
があり、反応すると二酸化炭素8とjcって除去できる
。さらに詳しく述べると、有機物ンζ紫外線を照射する
ことによりその分子結合を9〉解し、光分解反応で生成
した有機物のフリーラ7.−カルと、オゾンから発生し
た原子状の酸素が反1、.1−冊57、二酸化炭素、水
、窒素、酸素等のような単純へ分子を形成し気相化させ
て除去する。
It is also possible to perform surface treatment using only ozone 7 without UV irradiation. Ozone 7 has the effect of decomposing and removing organic matter, and when it reacts with carbon dioxide 8, it can be removed. More specifically, by irradiating the organic matter with ultraviolet rays, its molecular bonds are broken down, and the organic matter is freed from the photodecomposition reaction. -Cal and atomic oxygen generated from ozone are anti-1, . 1-Book 57, forms simple molecules such as carbon dioxide, water, nitrogen, oxygen, etc. and removes them by converting them into a gas phase.

次に第1図(C)に示すように、Alのエツチング族に
よって表面処理を行い下層配線酸化層4を除去する。A
/のエツチング族にはリン酸と硝酸の混合溶液を用い、
液温は35°C〜40℃で使用する。表面処理の時間は
下層配線酸化層4がごく薄いために30秒〜60秒程度
で十分である。ここでオーバーエツチングによって下層
配線5がエツチングされることは僅かにとどめておけば
問題とはならない。表面処理の後、純水洗浄を2段階以
上それぞれ数分間行い乾燥する。Alのエツチング族は
リン酸、リン酸と硝酸と酢酸の混合溶液、硝酸水溶液等
に置き換えることが可能である。
Next, as shown in FIG. 1C, surface treatment is performed using an etching group of Al to remove the lower wiring oxide layer 4. A
For the etching group of /, a mixed solution of phosphoric acid and nitric acid is used,
The liquid temperature is used at 35°C to 40°C. Since the lower wiring oxide layer 4 is extremely thin, a time of about 30 to 60 seconds is sufficient for the surface treatment. Here, etching of the lower layer wiring 5 due to over-etching will not be a problem as long as it is kept to a small extent. After the surface treatment, two or more stages of pure water cleaning are performed for several minutes each and then dried. The etching group of Al can be replaced with phosphoric acid, a mixed solution of phosphoric acid, nitric acid, and acetic acid, an aqueous nitric acid solution, or the like.

下層配線5としてA/以外の銅や高融点金属あるいはシ
リサイドを用いたときは、これらのエツチング液を用い
て下層配線酸化層4をエツチング除去する。
When copper, high melting point metal, or silicide other than A/ is used as the lower layer wiring 5, the lower layer wiring oxide layer 4 is etched away using these etching solutions.

下層配線酸化層4の除去は湿式エツチングであるために
水分の吸着が起こるが、真空乾燥処理を行うことによっ
てスルーホール1部の下層配線5表面を清浄に保ったま
ま脱水することができる。
Since the lower wiring oxide layer 4 is removed by wet etching, moisture adsorption occurs, but by performing a vacuum drying process, the surface of the lower wiring 5 in the through hole 1 can be dehydrated while being kept clean.

この真空乾燥の条件の1例を示すと、温度80℃〜11
0℃、時間30分〜60分、真空度l Torr程度あ
るいは次に記す上層配線9を形成するための装置内で真
空度10   Torr、温度200℃〜350℃、時
間20分程度の処理を行う。
An example of the vacuum drying conditions is a temperature of 80°C to 11°C.
Processing is carried out at 0°C, for 30 to 60 minutes, at a vacuum level of about 1 Torr, or at a vacuum level of 10 Torr, at a temperature of 200°C to 350°C, for about 20 minutes in a device for forming upper layer wiring 9 described below. .

本発明者の実験によると上記脱水方法として大気中乾燥
とN! (窒素)雰囲気乾燥と真空乾燥を試みた結果、
上層配線9と下層配線5の接続抵抗は真空乾燥法が最も
低抵抗で安定していることが確認された。
According to the inventor's experiments, the above dehydration methods include air drying and N! As a result of trying (nitrogen) atmosphere drying and vacuum drying,
It was confirmed that the connection resistance between the upper layer wiring 9 and the lower layer wiring 5 was the lowest and most stable when using the vacuum drying method.

次に第1図(d)に示すように、有機系被膜2と下層配
線酸化層4が除去された清浄な下層配線5上に上層配線
9を形成する。下層配線5と上層配線9の接続部には有
機系被膜2−?下層配線酸化層4の絶縁性被膜がなく、
電気的に導通の妨げになるものがないので低抵抗での接
続がなされる。
Next, as shown in FIG. 1(d), an upper layer wiring 9 is formed on the clean lower layer wiring 5 from which the organic film 2 and the lower layer wiring oxide layer 4 have been removed. An organic coating 2-? There is no insulating film of the lower wiring oxide layer 4,
Since there is nothing that prevents electrical continuity, the connection is made with low resistance.

〔発明の効果〕〔Effect of the invention〕

以上の説明で明らかなように、本発明の製造方法によれ
ば有機系被膜除去用にオゾン、下層配線酸化膜除去用に
その配線材料のエツチング液を用いて表面処理を行うこ
とによって、スルーホールの下層配線表面は清浄と九り
上層配線と下層配線の接続を低抵抗で行うことが可能と
なる。
As is clear from the above explanation, according to the manufacturing method of the present invention, through-holes can be formed by surface treatment using ozone to remove the organic film and an etching solution for the wiring material to remove the underlying wiring oxide film. Since the surface of the lower layer wiring is kept clean, it becomes possible to connect the upper layer wiring and the lower layer wiring with low resistance.

表面処理に真空装置を用いずに常圧下で処理できる比較
的安価なオゾン処理用の装置を用いることによって設備
は小規模となり、連続の処理が可能となるので処理効率
が向上する。オゾンは有機物を気体にして除去するので
装置内を汚染することはなく、真空系を持たないことか
らメンテナンスが容易にできる。
By using a relatively inexpensive ozone treatment device that can perform surface treatment under normal pressure without using a vacuum device, the equipment becomes small-scale and continuous treatment becomes possible, which improves treatment efficiency. Ozone removes organic matter by converting it into a gas, so it does not contaminate the inside of the device, and since it does not have a vacuum system, maintenance is easy.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(d)は本発明の表面処理方法を工程順
に示す断面図、第2図(a)〜(C)は従来例における
スパッタエツチング法を示す断面図である。 1・・・・・・スルーホール、 2・・・・・・有機系被膜、 6・・・・・・有機系樹脂膜、 4・・・・・・下層配線酸化層、 5・・・・・・下層配線、 6・・・・・・ウェハー 7・・・・・・オゾン、 8・・・・・・二酸化炭素、 9・・・・・・上層配線、 10・・・・・・Ar原子。 第1図 第2図
1A to 1D are cross-sectional views showing the surface treatment method of the present invention in the order of steps, and FIGS. 2A to 2C are cross-sectional views showing the conventional sputter etching method. 1...Through hole, 2...Organic coating, 6...Organic resin film, 4...Lower wiring oxide layer, 5... ...Lower layer wiring, 6...Wafer 7...Ozone, 8...Carbon dioxide, 9...Upper layer wiring, 10...Ar atom. Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 下層配線上に層間絶縁膜として絶縁性を有する有機系樹
脂膜を形成し、該有機系樹脂膜にスルーホールを形成後
上層配線を形成する半導体装置の製造方法において、前
記有機系樹脂膜に形成する前記スルーホール内の前記下
層配線表面をO_3(オゾン)による乾式エッチングと
前記下層配線のエッチング液による湿式エッチングにて
表面処理し、その後真空乾燥の工程を経て前記上層配線
を形成することを特徴とする半導体装置の製造方法。
In a method for manufacturing a semiconductor device, in which an organic resin film having insulating properties is formed as an interlayer insulating film on a lower layer wiring, a through hole is formed in the organic resin film, and then an upper layer wiring is formed. The surface of the lower layer wiring in the through hole is surface-treated by dry etching with O_3 (ozone) and wet etching with an etchant for the lower layer wiring, and then a vacuum drying process is performed to form the upper layer wiring. A method for manufacturing a semiconductor device.
JP21125489A 1989-08-18 1989-08-18 Manufacture of semiconductor device Pending JPH0376145A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21125489A JPH0376145A (en) 1989-08-18 1989-08-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21125489A JPH0376145A (en) 1989-08-18 1989-08-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0376145A true JPH0376145A (en) 1991-04-02

Family

ID=16602865

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21125489A Pending JPH0376145A (en) 1989-08-18 1989-08-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0376145A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999038208A1 (en) * 1998-01-22 1999-07-29 Citizen Watch Co., Ltd. Method of fabricating semiconductor device
JP2007108780A (en) * 1997-05-27 2007-04-26 Mitsubishi Electric Corp Contact hole forming method of active matrix substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007108780A (en) * 1997-05-27 2007-04-26 Mitsubishi Electric Corp Contact hole forming method of active matrix substrate
WO1999038208A1 (en) * 1998-01-22 1999-07-29 Citizen Watch Co., Ltd. Method of fabricating semiconductor device

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