JPH0376151A - Capacitive element - Google Patents

Capacitive element

Info

Publication number
JPH0376151A
JPH0376151A JP21228489A JP21228489A JPH0376151A JP H0376151 A JPH0376151 A JP H0376151A JP 21228489 A JP21228489 A JP 21228489A JP 21228489 A JP21228489 A JP 21228489A JP H0376151 A JPH0376151 A JP H0376151A
Authority
JP
Japan
Prior art keywords
film
electrode
capacitive
poly
capacitive element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21228489A
Other languages
Japanese (ja)
Inventor
Kohei Eguchi
江口 公平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP21228489A priority Critical patent/JPH0376151A/en
Priority to EP90115184A priority patent/EP0412514A1/en
Priority to US07/564,250 priority patent/US5083184A/en
Publication of JPH0376151A publication Critical patent/JPH0376151A/en
Pending legal-status Critical Current

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Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE:To obtain a capacitive element in which no electric characteristics change with the alteration of positive and negative electricity in bias voltage by connecting the 1st electrode to the 4th one and the 2nd electrode to the 3rd one respectively and using the device as one capacitive element. CONSTITUTION:A capacitive film making up the 1st capacitive element C1 is composed of two layers, i.e., SiO2 51 and SiN films 61, and is sandwiched by two electrode, poly-Si films 31 and 61 and then, the poly-Si film 31 is connected to an Al film 91 and the poly-Si film 61 is connected to an Al film 92 through an aperture 101. Further, the capacitive film making up the 2nd capacitive element C2 is composed of two layers, SiO2 and SiN films 52 and 62 and is sandwiched by two electrodes, poly-Si films 32 and 62 and then, the poly-Si film 32 is connected to the Al film 92 and the poly-Si film 62 is connected to the Al film 91 through an aperture 102. Since these capacitive elements are placed in symmetry between two electrodes, the capacitive element is obtained wherein electric characteristics are not changed at all even though each bias voltage that is impressed positively or negative to the electrodes at both ends of this element is replaced with each other.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は容量素子に関し、特に集積回路に組み込まれる
容量素子に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a capacitive element, and particularly to a capacitive element incorporated into an integrated circuit.

〔従来の技術〕[Conventional technology]

従来半導体集積回路に組み込まれている容量素子の一例
を第2図(a)、 (b)を用いて説明する。第2図(
b)に示すように容量膜はSiO2膜5とSiN膜6の
2層の誘電体膜から或っている。これをはさむ下部電極
3と上部電極7はいずれもPドープされたpoly−3
i(多結晶シリコン)から成っている。下部電極3はA
A膜9に接続され、また上部電極4はPSGSaO2孔
部10から他のA4膜へ接続されている。
An example of a capacitive element conventionally incorporated into a semiconductor integrated circuit will be described with reference to FIGS. 2(a) and 2(b). Figure 2 (
As shown in b), the capacitive film consists of two dielectric films, an SiO2 film 5 and a SiN film 6. The lower electrode 3 and upper electrode 7 sandwiching this are both P-doped poly-3
i (polycrystalline silicon). The lower electrode 3 is A
The upper electrode 4 is connected to the A4 film 9 through the PSGSaO2 hole 10.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の容量素子では、両端の電極に印加するバ
イアス電圧の正負を逆にすると容量値及びリーク電流値
の電気的特性が異なるという問題点がある。この原因は
特定できないが、下部及び上部電極の各々誘電体膜界面
の状態(例えば荒さ)の違い、第2図の例の様に容量膜
が複数の誘電体膜から形成されている場合、両鍔電体膜
材料のバンドギャップの違いによる電子の注入効率の違
い等に起因しているものと推定される。
The conventional capacitive element described above has a problem in that when the polarity of the bias voltage applied to the electrodes at both ends is reversed, the electrical characteristics of the capacitance value and the leakage current value differ. The cause of this cannot be determined, but it may be due to differences in the condition (e.g. roughness) of the interface between the dielectric films of the lower and upper electrodes, or when the capacitive film is formed from multiple dielectric films as in the example in Figure 2. This is presumed to be due to differences in electron injection efficiency due to differences in the band gaps of the flange electrode film materials.

本発明の目的は、複数の誘電体膜から構成される容量素
子において、バイアス電圧の正負の変化により電気的特
性が変化することがない容量素子を提供することにある
An object of the present invention is to provide a capacitive element composed of a plurality of dielectric films whose electrical characteristics do not change due to changes in positive or negative bias voltage.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の容量素子は、第1の電極と前記第1の電極上に
設けられた第1の誘電体膜と前記第1の誘電体膜上に設
けられた第2の誘電体膜と前記第2の誘電体膜上に設け
られた第2の電極とからなる第1の容量素子と、少なく
とも前記第1の電極と同材質の第3の電極と前記第3の
電極上に設けられた前記第1の誘電体膜と同材質の第3
の誘電体膜と前記第3の誘電体膜上に設けられた前記第
2の誘電体膜と同材質の第4の誘電体膜と前記第4の誘
電体膜上に設けられた少なくとも前記第2と電極と同材
質の第4の電極とからなる第2の容量素子とを有し、前
記第1の電極と前記第4の電極とを接続し電気第2の電
極と前記第3の電極とを接続することにより1つの容量
素子として用いることを特徴とする。
The capacitive element of the present invention includes a first electrode, a first dielectric film provided on the first electrode, a second dielectric film provided on the first dielectric film, and a first dielectric film provided on the first electrode. a first capacitive element consisting of a second electrode provided on a second dielectric film; a third electrode made of at least the same material as the first electrode; and a third electrode provided on the third electrode. A third dielectric film made of the same material as the first dielectric film.
a fourth dielectric film made of the same material as the second dielectric film provided on the third dielectric film, and at least the fourth dielectric film provided on the fourth dielectric film. 2 and a fourth electrode made of the same material as the electrode, the first electrode and the fourth electrode are connected, and the second electrode and the third electrode are connected. It is characterized in that it is used as one capacitive element by connecting them.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)、 (b)は本発明の第1の実施例を説明
するための平面図及び縦断面図である。第1図(a)に
示すように、Si基板1上には100000000A厚
22があり、その上に5000A厚のPドープpoly
−8i(多結晶シリコン)膜31.32.更に5000
A厚のPSG膜4.100A厚のS i O2膜51,
52,100A厚のSiN膜61,62,500.0大
要のPドーフpoly−8i膜71,72.5000A
厚のPSGSaO2μm厚のA(膜91,92がバター
ニングされている。
FIGS. 1(a) and 1(b) are a plan view and a longitudinal sectional view for explaining a first embodiment of the present invention. As shown in FIG. 1(a), there is a 100000000A thickness 22 on the Si substrate 1, and a 5000A thick P-doped polyester is placed on top of it.
-8i (polycrystalline silicon) film 31.32. Another 5000
A-thick PSG film 4.100A-thick SiO2 film 51,
52,100A thick SiN film 61,62,500.0 P Dorf poly-8i film 71,72.5000A
PSGSaO 2 μm thick A (films 91 and 92 are patterned).

第1の容量素子C1を構成している容量膜は5i02膜
51とSiN膜61の2層からなり、poly−3i膜
31とpoly−3i膜61の2つの電極にはさまれて
いる。poly−3i膜31はAff膜91に接続され
、poly−8i膜61はPSGSaO2孔部101を
介してAn膜92に接続されている。5iOz膜51の
下のPSG膜4の開孔面積は1000μmlである。も
う一方の第2の容量素子C2を構成している容量膜は5
i(h膜52とSiN膜62の2層からなり、poly
−3i膜32とpoly−8i膜62の2つの電極には
さまれており、poly−3i膜32はA、ff膜92
に接続され、poly−8i膜62はPSGSaO2孔
部102を介してA1膜91に接続されている。5if
2膜52の下のPSG膜4、の開孔面積は1000μm
lである。このように、CIを構成する一方の容量膜と
02を構成するもう一方の容量膜は、上部電極と下部電
極が互いに交差して並列に接続されていることになり、
これら全てで、容量膜として5iChlOO人、5iN
100人の2層が重なった面積2000μポの1つの容
量素子として用いることができる。
The capacitive film constituting the first capacitive element C1 is composed of two layers, a 5i02 film 51 and a SiN film 61, and is sandwiched between two electrodes, a poly-3i film 31 and a poly-3i film 61. The poly-3i film 31 is connected to the Aff film 91, and the poly-8i film 61 is connected to the An film 92 via the PSGSaO2 hole 101. The open pore area of the PSG film 4 under the 5iOz film 51 is 1000 μml. The capacitive film constituting the other second capacitive element C2 is 5
It consists of two layers, i(h film 52 and SiN film 62, and is made of poly
-3i film 32 and poly-8i film 62, the poly-3i film 32 is A, ff film 92
The poly-8i film 62 is connected to the A1 film 91 via the PSGSaO2 hole 102. 5if
The open pore area of the PSG film 4 under the second film 52 is 1000 μm.
It is l. In this way, one capacitive film constituting CI and the other capacitive film constituting 02 are connected in parallel with the upper electrode and lower electrode crossing each other.
In all of these, 5iChlOO people and 5iN as capacitive membranes.
It can be used as one capacitive element with an area of 2000 μm made by overlapping two layers of 100 people.

このように本実施例によれば、複数の異なる材質からな
る容量膜を有する2つの容量素子を設け、互いに異なっ
た材質の容量膜に面している電極同士を接続して1つの
容量素子として用いるため、容量膜の材質のちがいから
起因する電気的特性は相殺されることになる。
As described above, according to this embodiment, two capacitive elements each having a capacitive film made of a plurality of different materials are provided, and the electrodes facing the capacitive films made of different materials are connected to form one capacitive element. Therefore, the electrical characteristics caused by the difference in the material of the capacitive film are canceled out.

第2の実施例は、第1の実施例における第1図の100
A厚の5ift膜51.52を各4100A厚のSiN
膜に置きかえ、また100A厚のSiN膜61,62を
各々500A厚のT&205膜に置き換えたものである
。その他の構造については第1の実施例と同様とする。
The second embodiment is 100 in FIG. 1 in the first embodiment.
A 5ift film 51.52 with a thickness of 4100A each
In addition, the 100A thick SiN films 61 and 62 are each replaced with 500A thick T&205 films. The other structures are the same as those in the first embodiment.

すると、容量膜として5i膜100人厚、Tags膜5
00人の2層が重なった面積200μmlの容量素子が
得られ、第1の実施例と同様な効果が得られる。
Then, as a capacitive film, a 5i film with a thickness of 100 mm and a Tags film with a thickness of 5
A capacitive element having an area of 200 μml in which two layers of 0.00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 layers overlapped layers overlap each other and the first embodiment can be obtained.

〔発明の効果〕 以上説明した様に、本発明による容量素子は並列に接続
されたそれぞれ材質の異なる二層と容量膜を有する2つ
の容量素子からなり、各々の異なった材質に面した下部
電極と上部電極が互いに交差して接続されている。従っ
て本発明の容量素子は構造的に両電極間で全く対称にな
っているため、両端の電極へ印加するバイアス電圧を正
負逆に入れ替えたとしてもその電気的特性は全く変わら
ないという効果を有している。
[Effects of the Invention] As explained above, the capacitive element according to the present invention consists of two capacitive elements connected in parallel, each having two layers and a capacitive film made of different materials, and a lower electrode facing each different material. and upper electrodes are connected to cross each other. Therefore, since the capacitive element of the present invention is structurally completely symmetrical between the two electrodes, it has the effect that its electrical characteristics do not change at all even if the bias voltage applied to the electrodes at both ends is reversed. are doing.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)、 (b)は本発明の第1の実施例を説明
するための平面図及び縦断面図、第2図(a)。 (b)は従来例を説明するための平面図及び縦断面図で
ある。 1・・・・・・Si基板、2,5,51.52・・・・
・・5in2膜、3,31,32,7,71.72・・
・・・・poly−3i膜、4,8・・・・・・PSG
膜、6,61.62・・・・・・SiN膜、9,91.
92・・・・・・AI2膜、10゜101.102・・
・・・・開孔部。
FIGS. 1(a) and 1(b) are a plan view and a vertical cross-sectional view for explaining a first embodiment of the present invention, and FIG. (b) is a plan view and a vertical sectional view for explaining a conventional example. 1... Si substrate, 2, 5, 51.52...
・・5in2 membrane, 3, 31, 32, 7, 71.72・・
...poly-3i film, 4,8...PSG
Film, 6,61.62...SiN film, 9,91.
92...AI2 membrane, 10°101.102...
...Open hole.

Claims (1)

【特許請求の範囲】[Claims]  第1の電極とこの第1の電極上に設けられた第1の誘
電体膜とこの第1の誘電体膜上に設けられた第2の誘電
体膜とこの第2の誘電体膜上に設けられた第2の電極と
からなる第1の容量素子と、少なくとも前記第1の電極
と同材質の第3の電極とこの第3の電極上に設けられた
前記第1の誘電体膜と同材質の第3の誘電体膜とこの第
3の誘電体膜上に設けられた前記第2の誘電体膜と同材
質の第4の誘電体膜とこの第4の誘電体膜上に設けられ
少なくとも前記第2の電極と同材質の第4の電極とから
なる第2の容量素子とを有し、前記第1の電極と前記第
4の電極とを接続し前記第2の電極と前記第3の電極と
を接続することにより1つの容量として用いることを特
徴とする容量素子。
A first electrode, a first dielectric film provided on the first electrode, a second dielectric film provided on the first dielectric film, and a second dielectric film provided on the second dielectric film. a first capacitive element comprising a second electrode provided, a third electrode made of at least the same material as the first electrode, and the first dielectric film provided on the third electrode; a third dielectric film made of the same material; a fourth dielectric film made of the same material as the second dielectric film provided on the third dielectric film; and a fourth dielectric film provided on the fourth dielectric film. and a second capacitive element consisting of at least a fourth electrode made of the same material as the second electrode, the first electrode and the fourth electrode are connected, and the second electrode and the fourth electrode are connected to each other. A capacitor element characterized in that it is used as one capacitor by connecting it to a third electrode.
JP21228489A 1989-08-08 1989-08-18 Capacitive element Pending JPH0376151A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP21228489A JPH0376151A (en) 1989-08-18 1989-08-18 Capacitive element
EP90115184A EP0412514A1 (en) 1989-08-08 1990-08-07 Capacitance device
US07/564,250 US5083184A (en) 1989-08-08 1990-08-08 Capacitance device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21228489A JPH0376151A (en) 1989-08-18 1989-08-18 Capacitive element

Publications (1)

Publication Number Publication Date
JPH0376151A true JPH0376151A (en) 1991-04-02

Family

ID=16620054

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21228489A Pending JPH0376151A (en) 1989-08-08 1989-08-18 Capacitive element

Country Status (1)

Country Link
JP (1) JPH0376151A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002078024A1 (en) * 2001-03-16 2002-10-03 Hitachi, Ltd. Thin film capacitor and thin film electronic component and method for fabricating the same
CN100454650C (en) * 2003-11-28 2009-01-21 松下电器产业株式会社 Energy device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002078024A1 (en) * 2001-03-16 2002-10-03 Hitachi, Ltd. Thin film capacitor and thin film electronic component and method for fabricating the same
CN100454650C (en) * 2003-11-28 2009-01-21 松下电器产业株式会社 Energy device and manufacturing method thereof

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