JPH0376318A - Delta-sigma modulation circuit in digital/analog converter or analog/digital converter - Google Patents

Abstract

PURPOSE:To make the operation stable and to expand the dynamic range by approaching the degree of an integration circuit to a characteristic of the quadratic order when signal level is high, and approaching the degree of the integration circuit to a characteristic of the 3rd order when signal level is low. CONSTITUTION:The relation of input and output signals of a delta-sigma modulation circuit 3 is expressed in equation I, where X, Y are input and output signals, Q is quantization noise, A is a multiplication gain of a variable multiplier 11 and Z<-1> is a sample delay of a delay device 14. With A=0 set, the degree of an integration circuit reaches a characteristic of quadratic degree as Y=X+Q(1-Z<-1>)<2> and with A=1 set, the degree of the integration circuit reaches a characteristic of 3rd degree as Y=X+Q(1-Z<-1>)<3>. For example, assuming as A=1/256 until input levels of 0--4dB, as A=1/16 until input levels of -4dB--8dB, and as A=1/8 until input level of <=-8dB, then, the degree of the integration circuit approaches the quadratic when the input level is high and its operation is made stable. When the input level is -10dB or below, the dynamic range is increased.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an oversampling digital/analog converter (hereinafter referred to as a D/A converter) used for applications such as digital audio and communication. The present invention relates to a delta-sigma modulation circuit in an analog/digital converter (hereinafter referred to as an A/D converter).

[Prior Art] Generally, an oversampling type D/A converter is composed of an interpolation digital filter circuit, a noise shaver, and a local D/A converter. consists of a noise shaver and a decimation digital filter circuit.

Of these, the oversampling type D/A is representative.
Briefly explaining the operation of the converter, first, in the interpolation digital filter circuit, the sampling frequency of the input digital signal is increased (that is, oversampled) and then filtered. Next, in the noise shaver, the noise distribution of the quantization noise of the filtered digital signal is changed. Next, the local D/A converter converts the digital signal with the changed noise distribution into an analog signal.

Here, various circuits are used as the noise shaver, and one of them is a delta-sigma modulation circuit.

A delta-sigma modulation circuit is mainly composed of a feedback loop consisting of one or more integrating circuits, a quantizer, and a delay device.

Generally, the following three methods are known for increasing the dynamic range of a D/A converter or an A/D converter that uses a delta-sigma modulation circuit as a noise shaver.

The first is to increase the order of oversampling (that is, to increase the sampling frequency relative to the Nyquist frequency), and the second is to increase the oversampling order (that is, increase the sampling frequency with respect to the Nyquist frequency). The third method is to increase the order (that is, increase the number of integrating circuits), and the third method is to increase the number of bits of the quantizer that constitutes the delta-sigma modulation circuit.

If the first method is to increase the order of oversampling, it is necessary to increase the operating speed of each circuit accordingly, but even if the operating speed is increased, the circuit elements of each circuit Each has its own operating speed limit. Therefore, the order of oversampling cannot be made very high.

In addition, if the second method is to increase the order of the integrator circuit in the feedback loop that constitutes the delta-sigma modulation circuit, the order of the integrator circuit in the feedback loop will increase up to the second order (i.e., the number of integrator circuits However, when the order of the integrating circuit becomes 3rd order or higher (that is, the number of integrating circuits becomes 3 or more), oscillation occurs, which is a problem.

Therefore, conventionally, in order to solve the problems when using the second method, for example, Japanese Patent Application Laid-Open No. 63-20933
As described in Publication No. 4, Nvt is a first-order or second-order feedback loop in which the order of the integrating circuit in the loop is stable.
Equivalently, a delta-sigma modulation circuit that operates stably when the order of the integrating circuit is 3rd or higher was realized.

Further, as a third example of a previously proposed method of increasing the number of bits of the quantizer constituting the delta-sigma modulation circuit, there is, for example, Japanese Patent Laid-Open No. 62-269423.

[Problem to be solved by the invention]

As mentioned above, in the former proposed example, equivalently,
The dynamic range is increased by increasing the order of the integrating circuit to third or higher, and in the latter example, by increasing the number of bits of the quantizer. be able to.

However, in the two previously proposed examples of θ, the quantized value (
In other words, since the number of bits (bit number) becomes more than 1 bit, for example, in the case of a D/A converter using a delta-sigma modulation circuit, the bit number of the local D/A converter connected after the delta-sigma modulation circuit The number must also be greater than l bits.

However, for example, when obtaining a dynamic range with 16-bit precision, even if the number of bits (resolution) of the local D/A converter is 3 bits, 16-bit precision is required for the integral error (nonlinear error). be done. However, in reality, it is very difficult to fabricate such a local D/A converter when considering the conversion of CMOS process to l-chip LSI.

Therefore, in the latter proposed example, a multilevel D/A converter composed of a PWM converter and a low-pass filter is used as the local A/D converter, but it requires a high clock frequency or , "Hl", and "LO" and the constant of the low-pass filter, there is a problem in that high-order harmonics are likely to be generated.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned problems of the prior art, and to provide an integrated circuit in which the order of the integrating circuit is 3rd order or higher, and the quantization value (i.e., the number of bits) of the output digital signal is less than 1 bit. It is an object of the present invention to provide a delta-sigma modulation circuit that can operate stably without increasing the number of circuits.

(Means for Solving the Problems) In order to achieve the above-mentioned object, in the present invention, when used in an oversampling D/A converter, a delta-sigma modulation circuit is configured to integrate three or more cascaded integrals. a subtracter that subtracts the output signal of the delay device from the input signal of the delta-sigma modulation circuit and inputs the obtained subtracted signal to a first-stage integration circuit of the cascade-connected integration circuits; , a variable multiplier that multiplies the output signal of each of the third or higher stages of the integrating circuits connected in cascade by a multiplication value, and outputs the obtained multiplied signal, and at least
an adder that adds the multiplied signal and the output signal of the second-stage integrating circuit of the cascade-connected integrating circuits and outputs the obtained added signal; It consists of at least a quantizer that outputs an output signal of the delta-sigma modulation circuit, and the delay device that delays and outputs the output signal of the quantizer, and the input signal and output of the interpolation digital filter circuit. The multiplication value of the variable multiplier is changed according to the output signal of a level detector that detects the level of either the signal or the output signal of the local D/A converter and outputs the detection result. I did it like that.

When used in an oversampling A/D converter, in the delta-sigma modulation circuit, an internal circuit that converts the output signal of the delay device into an analog signal is provided in the signal path from the delay device to the subtracter. A digital/analog converter is provided, and the level detector detects the level of either the input signal of the delta-sigma modulation circuit or the output signal of the decimation digital filter circuit.

[Effect]

The present invention focuses on the fact that when the order of the integrating circuit is third or higher, the higher the signal level, the more likely it is to oscillate, and the more unstable the operation becomes.

That is, when the level detector detects that the level of the signal is relatively large, oscillation is likely to occur;
The multiplication value of the variable multiplier is changed to become smaller.

As a result, the delta-sigma modulation circuit approaches the characteristic when the order of the integrating circuit is second order, does not oscillate, and becomes stable in operation.

Conversely, when the level detector detects that the level of the signal is relatively low, it is difficult to oscillate, so the multiplication value of the variable multiplier is changed to increase. As a result, the characteristics of the delta-sigma modulation circuit approach those of the case where the order of the integration circuit is third or higher, and the dynamic range becomes large.

Therefore, according to the present invention, the dynamic range can be increased while operating stably.

In addition, since the number of bits of the quantizer is only 1 bit, the quantization value (i.e., number of bits) of the digital signal output from the delta-sigma modulation circuit is also 1 bit, and the oversampling D/A converter In this case, the number of bits of the local D/A converter connected after the delta-sigma modulation circuit may also be 1 bit. Therefore, for example, even if 16-bit accuracy is required, it is fully possible to convert the CMOS process into 1 chip [,31]. In addition, the oversampling method A/
In the case of a D converter, the number of bits of the internal D/A converter to which the output signal of the quantizer is input via the delay device may be 1 bit.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an oversampling type D/A converter using a delta-sigma modulation circuit as a first embodiment of the present invention.

In FIG. 1, l is an input terminal, 2 is an interpolation digital filter circuit, 3 is a delta-sigma modulation circuit, 4 is a local D/A converter, 5 is an output terminal, and 6 is a level detector. Note that the delta-sigma modulation circuit 3 includes a subtracter 7, an integrating circuit 8°9.10, a variable multiplier 11, an adder 12, a quantizer 13, and a delay device 14. . Further, Q is quantization noise of the quantizer 13.

Now, the operation of the D/A converter shown in FIG. 1 will be schematically explained.

First, a digital signal input from an input terminal 1 is passed through an interpolation digital filter circuit 2.
After interpolation and increasing the sampling frequency (ie, oversampling), filtering is performed. next,
In the delta-sigma modulation circuit 3, the noise distribution of quantization noise of the filtered digital signal is changed.

Next, the local D/A converter 4 converts the digital signal with the changed noise distribution into an analog signal. The converted analog signal is output from the output terminal 5.

Note that the operation of each circuit in the delta-sigma modulation circuit 3 and the operation of the level detector 6 will be described later.

Next, FIG. 2 shows an oversampling A/D using a delta-sigma modulation circuit as a second embodiment of the present invention.
FIG. 2 is a block diagram showing a converter.

In FIG. 2, the same parts as in FIG. 1 are given the same reference numerals. Additionally, 3' is a delta-sigma modulation circuit, 15 is an internal D/A converter, and 16 is a decimation digital filter circuit. Note that the delta-sigma modulation circuit 3'' has almost the same configuration as the delta-sigma modulation circuit 3 shown in FIG. An internal D/A converter 15 is inserted to convert digital signals into analog signals.

Now, the operation of the A/D converter shown in FIG. 2 will be schematically explained.

First, the analog signal input from the input terminal 1 is converted into a digital signal in the delta-sigma modulation circuit 3'' while changing the noise distribution of quantization noise.Next, in the decimating digital filter circuit 16,
The converted digital signal is decimated and filtered. The filtered digital signal is output from the output terminal 5.

Note that the operation of each circuit within the delta-sigma modulation circuit 3° and the operation of the level detector 6 will be described later.

Now, the delta-sigma modulation circuits 3 and 3 in FIGS. 1 and 2
Before explaining the operation of each of the circuits within 1.degree. and the operation of the level detector 6, a basic delta-sigma modulation circuit will be briefly explained.

Fig. 3 is a block diagram showing a basic delta-sigma modulation circuit in which the order of the integrating circuit is 2nd order, and Fig. 4 is a block diagram showing a basic delta-sigma modulation circuit in which the order of the integrating circuit is 3rd order. .

In these figures, the same parts as in FIG. 1 are given the same reference numerals. Additionally, 31 and 32 are subtracters.

In the delta-sigma modulation circuit shown in FIG. 3 in which the order of the integration circuit is second order, the input signal is X, the output signal is Y, the quantization noise of the quantizer 13 is Q, and the l sample delay of the delay device 14 is Z. -1, the transfer characteristic is calculated using the Z function as Y = X 10(1-Z-')" -Q
It can be expressed as ...-(1).

On the other hand, the delta-sigma modulation circuit in which the order of integration shown in Fig. 4 is 3rd order actually oscillates and cannot be put to practical use as it is, but its theoretical transfer characteristic is Y-X+(1-Z-')
'・Q ......(2).

This is because here Z-'=e-'''t.

Now, if the original sampling frequency is fs,
When oversampling is performed by a factor of 0M so that the passband is f,/2, the sampling frequency is expressed as M−f.

Therefore, in a delta-sigma modulation circuit where the order of the integrating circuit is second order, the quantization noise Q is (1-Z-')''.

In a delta-sigma modulation circuit where the order of the integrating circuit is 3rd order (1
-Z-')' is applied as a coefficient, so the spectrum of the quantization noise is shown in FIG. 5.

As is clear from FIG. 5, compared to the original white noise, it is suppressed in the low range and expanded in the high range. The operation of changing the noise distribution of quantization noise in this way is called noise shaving. It can be seen that noise is sufficiently suppressed in the passband f,/2.

Next, the dynamic range (equivalent to the S/N ratio) within the f3/2 band is calculated.

First, the quantization noise is spread by oversampling by M times, and the noise power becomes 1/M for the band f,/2. Therefore, the number of bits of the quantizer 13 is set to N
, if the order of the integration circuit is ■, and the noise in the f3/2 band is approximated to triangular noise that decreases as the frequency goes down, we get
The dynamic range DR in the f,/2 band is: DR (dB) = 20 fog (2) + 1) -) 1.76
+10f! It becomes ogM.

Items 1 and 2 are terms for the number of quantization bits, item 3 is a term for improving the S/N ratio by oversampling by M times, and item 4 is a term for suppressing the frequency of f,/2 by noise shaving. 5 items are items for improving in-band noise by triangular noise approximation.

Here, when formula (5) is illustrated by plotting the order M of oversampling on the horizontal axis and the dynamic range DR (dB) on the vertical axis, it becomes as shown in FIG. 6.

In addition, in FIG. 6, the number of focuses N of the quantizer 13 is 1.

As is clear from FIG. 6, in 128 times oversampling, 16-bit precision cannot be obtained when the order of the integrating circuit is second order, but it can be obtained when the order is third order. In other words, the number of bits of the quantizer 13 is 1
When the oversampling order is 128 times in bits,
To obtain a dynamic range with 16-bit precision,
It can be seen that the order of the integrating circuit must be 3rd order or higher.

Therefore, the delta-sigma modulation circuit 3 of FIGS. 1 and 2.
The operation of each circuit within 3'' will be explained using the delta-sigma modulation circuit 3 in FIG. 1 as a representative.

FIG. 7 is a block diagram showing the delta-sigma modulation circuit of FIG. 1.

In FIG. 7, 17 is an input terminal of the delta-sigma modulation circuit, and 18 is an output terminal, and the input signal and output signal are X and Y, respectively. 8,9°10 is a first-order integrating circuit. Reference numeral 11 denotes a variable multiplier, and its multiplication value (ie, multiplication gain) is set to A, where A satisfies O≦A≦1. 1
2 is an adder.

Reference numeral 13 denotes a quantizer, the number of bits of which is 1, and its quantization noise is Q. 14 is a delay device;
The signal is delayed by one sample, that is, a time of 1/M·[S. 7 is a subtractor.

The relationship between the human output signals of the delta-sigma modulation circuit in Figure 7 is as follows: ・・・・・・(6) becomes. (6〉If we rearrange the formula, becomes. However, some An approximation was made.

In formula (7), when A=0, Y=X+Q (1-Z-')"...
...〈8) is the characteristic when the order of the integrating circuit is second order, and when it is 8-1, Y=X0Q (1-Z-')' ...
...(9) shows that the characteristic is obtained when the order of the integrating circuit is third.

Therefore, it can be seen that when Q<A<1, the order of the integrating circuit has a characteristic with a value intermediate between the second order and the third order.

FIG. 8 shows the results of calculating the dynamic range for the input level based on equation (7). In addition, in FIG. 8, the order M of oversampling is 128,
Further, A is of three types: 1/256.1/16.1/8.

As can be seen from FIG. 8, when A=1/16.1/8, oscillation occurs when the input level is 12 dB and -4 dB, respectively. Furthermore, when the input level is around 140 dB, the larger A becomes, the larger the dynamic range becomes.

Therefore, for example, if the input level is from O to -4 dB, A = , and from -4 dB to -8 dB.
Next, the operation becomes stable and the input level is -10 dB.
The dynamic range can be increased in the following cases.

Therefore, in order to change this A, that is, the multiplication value of the variable multiplier 11, a level detector 3 is provided in FIG. That is, the level detector 3 detects the level (ie, input level) of the input signal of the delta-sigma modulation circuit 3 7, and the multiplication of the variable multiplier 11 is switched according to the detection result. Here, the level detection 233 detects the level of the input signal by successively comparing the level of the input signal with a preset reference level.

On the other hand, in the delta-sigma modulation circuit 3'' shown in Fig. 2,
As mentioned above, since the signals handled are analog signals,
The internal D/A converter 15 converts the digital signal output from the delay device 4 into an analog signal, but apart from that point, the operation of the delta-sigma modulation circuit 3' shown in Fig. 2 is the same as that shown in Fig. 1. The operation is similar to that of the delta-sigma modulation circuit 3 shown in FIG.

Also, in FIG. 2, a level detector 3 is provided in order to vary the multiplication value A of the variable multiplier 11, but this level detector 3 detects the level of the output signal of the decimation digital filter circuit 16. The multiplier value A of the variable multiplier 11 is switched based on the detection result.

FIG. 9 is a block diagram showing an oversampling D/A converter using a delta-sigma modulation circuit as a third embodiment of the present invention, and FIG. 10 is a block diagram showing a delta-sigma modulation circuit as a fourth embodiment of the present invention. FIG. 2 is a block diagram showing an oversampling A/D converter using a sigma modulation circuit.

In these figures, the same parts as in FIGS. 1 and 2 are given the same reference numerals. In addition, 19 is a limiter circuit, 20.
20'' is a delta-sigma modulation circuit.

Delta-sigma modulation circuit 20゜20'' in Figures 9 and 10
In this case, a limiter circuit 19 is provided between the integrating circuit 10 and the variable multiplier 11, and by limiting the output signal of the integrating circuit 10 to within a limit value, oscillation becomes difficult and stabilization can be achieved. By switching the limit value of the limiter circuit 19 according to the detection result of the level detector 6, more fine-grained control is performed.

FIG. 11 is a block diagram showing an oversampling D/A converter using a delta-sigma modulation circuit as a fifth embodiment of the present invention, and FIG. 12 is a block diagram showing a delta-sigma modulation circuit as a sixth embodiment of the present invention. FIG. 2 is a block diagram showing an oversampling A/D converter using a sigma modulation circuit.

In these figures, the same parts as in FIGS. 1 and 2 are given the same reference numerals. Additionally, 21 is a timer device.

In FIGS. 11 and 12, a timer device 21 for measuring a certain period of time is connected to the level detector 6.

The level detector 6 detects the input signal of the delta-sigma modulation circuit 3 in FIG. 1, and the output signal of the decimation digital filter circuit 16 in FIG.
In each case, the level at each instant is sequentially detected, and the multiplier value A of the variable multiplier 11 is switched according to the detection result, but in FIGS. The maximum level of is detected, and the multiplication value A of the variable multiplier 11 is switched based on the detection result. Therefore, the multiplication value A of the variable multiplier 11 is switched quasi-instantaneously.

FIG. 13 is a block diagram showing an oversampling type D/A converter using a delta-sigma modulation circuit as a seventh embodiment of the present invention.

In FIG. 13, the same parts as in FIG. 1 are given the same reference numerals.

In FIG. 13, the level detector 6 detects the level of the input signal of the interpolation digital filter circuit 2, and switches the multiplication value A of the variable multiplier 11 based on the detection result.

Even in this case, the same effect as in FIG. 1 can be obtained.

FIG. 14 is a block diagram showing an oversampling type A/D converter using a delta-sigma modulation circuit as an eighth embodiment of the present invention.

In FIG. 14, the same parts as in FIG. 2 are given the same reference numerals.

In FIG. 14, the level detector 6 detects the level of the input signal of the delta-sigma modulation circuit 3', which is an analog signal, and switches the multiplication value A of the variable multiplier 11 based on the detection result.

Even in this case, the same effect as in FIG. 2 can be obtained.

FIG. 15 is a block diagram showing a delta-sigma modulation circuit as a ninth embodiment of the present invention, and FIG. 16 is a block diagram showing a delta-sigma modulation circuit as a ninth embodiment of the present invention.
FIG. 17 is a block diagram showing a delta-sigma modulation circuit as an eleventh embodiment of the present invention.

In these figures, the same parts as in FIG. 7 are given the same reference numerals. Additionally, 22 and 23 are adders, and 24 is a subtracter.

In the delta-sigma modulation circuits shown in FIGS. 15, 16, and 17, the relationship between the human output signals is similar to the approximate equation (7). Therefore, FIG.

It can be used as a delta-sigma modulation circuit in the oversampling type D/A converter shown in FIGS. 9, 11, and 13.

In addition, if the internal D/A converter 15 is provided, FIG.
It can also be used as a delta-sigma modulation circuit in the oversampling type A/D converter shown in FIGS. 0, 12, and 14.

In this way, in the case of a delta-sigma modulation circuit in which the order of the integrating circuit is 3rd order, it can be developed into various circuits.

FIG. 18 is a block diagram showing a delta-sigma modulation circuit as a twelfth embodiment of the present invention.

In FIG. 18, the same parts as in FIG. 1 are given the same reference numerals. Additionally, 25 is a first-order integrating circuit. 26 and 27 are variable multipliers, the multiplier value of the variable multiplier 26 is AI, and the multiplier value of the variable multiplier 27 is A2.

The delta-sigma modulation circuit shown in FIG. 18 is a delta-sigma modulation circuit in which the order of the integration circuit is fourth.

The transmission formula in this case is ・・・・・・(10) becomes.

In the equation (lO), when A = O, Az = o, the characteristic is when the order of the integrating circuit is second order, and A.

=1. When A, = 0, the characteristic is that when the order of the integrating circuit is 3rd order, and A, = 1. When At = 1, the characteristic is the case where the order of the integrating circuit is 4th order.

Therefore, by switching the multiplication value A+ of the variable multiplier 26 and the multiplication value A2 of the variable multiplier 27 according to the detection result of the level detector 6, it is similar to the delta-sigma modulation circuit in which the order of the integration circuit is 3rd order. effect can be obtained.

Furthermore, it goes without saying that a delta-sigma modulation circuit in which the order of the integrating circuit is fourth can be developed into various circuits in the same manner as in the case of a third-order delta-sigma modulation circuit.

〔Effect of the invention〕

According to the present invention, even if the order of the integrating circuit is third or higher, the signal (i.e., in the case of a D/A converter, the input signal of the interpolation digital filter circuit, the output signal or the local D/A conversion In the case of an A/D converter, this is the input signal of the delta-sigma modulation circuit or the output signal of the decimation digital filter circuit. By approaching the characteristics in the following cases, and approaching the characteristics in the case where the order of the integrating circuit is 3rd order or higher when the level is small, it is possible to stabilize the operation by preventing oscillation when the level is large. At the Psi level, the dynamic range can be expanded. Therefore,
The dynamic range can be increased while operating stably.

In other words, when obtaining the same dynamo G range, the oversampling order can be lowered compared to a conventional delta-sigma modulation circuit where the integration circuit has a second-order order, so the operating speed of each circuit can be reduced. can be reduced.

Furthermore, since the number of bits of the quantizer is only l bits, the foster value (i.e., the number of bits) of the digital signal output from the delta-sigma modulation circuit is also 1 bit, and the D/
In the case of an A converter, the number of bits of the local D/A converter connected after the delta-sigma modulation circuit may also be 1 bit. Therefore, for example, even if 16-bit precision is required, CMO
It becomes possible to convert the S process into a one-chip LSI.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an oversampling D/A converter using a delta-sigma modulation circuit as a first embodiment of the invention, and FIG. 2 is a block diagram showing a second embodiment of the invention. A block diagram showing an oversampling A/D converter using a delta sigma modulation circuit, Fig. 3 is a block diagram showing a basic delta sigma modulation circuit in which the order of the integrating circuit is second order, and Fig. 4 FIG. 5 is a block diagram showing a basic delta-sigma modulation circuit in which the order of the integration circuit is third; FIG. 5 is a characteristic diagram showing the relationship between frequency and quantization noise level in the delta-sigma modulation circuit according to the present invention; and FIG. The figure is a characteristic diagram showing the relationship between the order of oversampling and the dynamic range in the delta-sigma modulation circuit according to the present invention, FIG. 7 is a block diagram showing the delta-sigma modulation circuit of FIG. 1, and FIG. FIG. 9 is a characteristic diagram showing the relationship between the input level and the dynamic range in the delta-sigma modulation circuit of the third embodiment of the present invention. A block diagram showing an oversampling A/Di converter using a delta-sigma modulation circuit as a fourth embodiment of the present invention, No. 1
FIG. 1 is a block diagram showing an oversampling D/A converter using a delta-sigma modulation circuit as a fifth embodiment of the present invention, and FIG. 12 is a block diagram showing a delta-sigma modulation circuit as a sixth embodiment of the present invention. A block diagram showing an over-sampling type A/D converter using a modulation circuit, and FIG. 13 is a block diagram showing an over-sampling type A/D converter using a delta-sigma modulation circuit as a seventh embodiment of the present invention. FIG. 14 is a block diagram showing an oversampling system using a delta-sigma modulation circuit as the eighth embodiment of the present invention.
, /D converter, FIG. 15 is a block diagram showing a delta-sigma modulation circuit as a ninth embodiment of the present invention, and FIG. 16 is a block diagram showing a delta-sigma modulation circuit as a ninth embodiment of the present invention. FIG. 17 is a block diagram showing the delta-sigma modulation circuit in columns 1 to L of the eleventh embodiment of the present invention, and FIG. 18 is a block diagram showing the delta-sigma modulation circuit in the eleventh embodiment of the present invention
FIG. 2 is a block diagram showing a stiff delta-sigma modulation circuit as an embodiment of the present invention. Explanation of symbols 2...Interborage? Digital filter circuit 9. 3...Delta sigma modulation circuit, 4...Local circuit,
/A converter, 6... Level detector, 7... Subtractor,
8.9゜10...Integrator circuit, 11...Variable multiplier,
12... Adder, 13... Quantizer, 14... Delay device, 15... Internal D/A converter, 16... Decimation digital filter circuit.

Claims (1)

[Claims] 1. Interpolating a digital signal as an input signal, and
an interpolation digital filter circuit that filters and outputs the output signal; a delta-sigma modulation circuit that outputs the output signal of the digital filter circuit by changing the noise distribution of its quantization noise; and a delta-sigma modulation circuit that outputs the output signal of the delta-sigma modulation circuit A digital/analog converter comprising: a local digital/analog converter that converts the signal into an analog signal and outputs the signal; The output signal of the delay device is subtracted from the signal, and the obtained subtracted signal is
A subtracter input to the first stage of the cascaded integration circuits and an output signal of each of the third and higher stages of the cascaded integration circuits are each multiplied by a multiplication value. and a variable multiplier that outputs the obtained multiplied signal, and at least the output signal of the second stage of the integrating circuits connected in cascade with the multiplied signal, and the obtained added signal. a quantizer that quantizes the added signal and outputs it as an output signal of the delta-sigma modulation circuit; and a delay device that delays and outputs the output signal of the quantizer. and detects the level of any one of the input signal and output signal of the digital filter circuit and the output signal of the local digital/analog converter, and outputs the detection result as an output signal of a level detector. A delta-sigma modulation circuit in a digital/analog converter, wherein a multiplication value of the variable multiplier changes accordingly. 2. The delta-sigma modulation circuit according to claim 1,
In addition to providing a timer device to measure a certain period of time,
The level detector detects the maximum level of any one of the input signal and output signal of the digital filter circuit and the output signal of the local digital/analog converter within a certain period of time measured by the timer device. A delta-sigma modulation circuit in a digital/analog converter, which detects and outputs the detection result. 3. A delta-sigma modulation circuit that converts an input analog signal into a digital signal and outputs the digital signal by changing the noise distribution of its quantization noise, and thins out the output signal of the delta-sigma modulation circuit. and a decimation digital filter circuit that performs filtering and outputs, the delta-sigma modulation circuit includes three or more cascade-connected integration circuits, and a decimation digital filter circuit that filters and outputs the input analog signal. The output signal of the digital/analog converter is subtracted, and the obtained subtracted signal is sent to one of the cascaded integration circuits.
A variable device that multiplies the output signals of the subtracter input to the integrating circuit of the third stage and the output signals of the integrating circuits of the third stage and above of the cascade-connected integrating circuits by a multiplication value, and outputs the obtained multiplied signal. a multiplier; an adder that adds the multiplied signal and at least an output signal of a second-stage integrating circuit of the cascade-connected integrating circuits and outputs the obtained added signal; A quantizer that quantizes and outputs it as an output signal of the delta-sigma modulation circuit, a delay device that delays and outputs the output signal of the quantizer, and converts the output signal of the delay device into an analog signal and outputs it. and the internal digital/analog converter, which detects the level of one of the input signal of the delta-sigma modulation circuit and the output signal of the digital filter circuit, and outputs the detection result. A delta-sigma modulation circuit in an analog/digital converter, characterized in that a multiplication value of the variable multiplier changes depending on an output signal of a level detector. 4. The delta-sigma modulation circuit according to claim 3,
In addition to providing a timer device to measure a certain period of time,
The level detector detects the maximum level of one of the input signals of the delta-sigma modulation circuit and the output signal of the digital filter circuit within a certain period of time measured by the timer device, and A delta-sigma modulation circuit in an analog/digital converter characterized by outputting a detection result. 5. The delta-sigma modulation circuit according to claim 1, 2, 3 or 4, further comprising: a variable limiter circuit for limiting the level of the input signal of the variable multiplier within a limit value; A delta-sigma modulation circuit characterized in that the signal is changed according to the output signal of the level detector.