JPH0376427A - Pll circuit - Google Patents

Abstract

PURPOSE:To omit the excess operation of a PLL circuit and to stabilize the PLL loop quickly by not applying power to a variable frequency divider and a phase comparator till an output reference signal of a reference signal oscillator and a fixed frequency divider is stabilized so as to inactivate the PLL loop from the variable frequency divider till the VCO. CONSTITUTION:A delay circuit 11 retards a voltage applied from a power supply voltage terminal 1 so as not to be fed to a variable frequency divider 6 and a phase comparator 7 till a reference signal oscillator 4 and a fixed frequency divider 5 are stabilized and an output reference signal from the fixed frequency divider 5 is stabilized. An output reference signal of the fixed frequency divider 5 is stabilized at first by inserting the delay circuit 11 to apply PLL operation from the variable frequency divider 6 to the VCO 9, and then excess operation of the variable frequency divider 6 to the VCO 9 is prevented till the output reference signal of the fixed frequency divider 5 is stabilized and low power consumption for that period is attained.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to an intermittent operation PLL (Phare Locked Loo) used to reduce power consumption.
[Prior art] Figure 2 is a block diagram of a conventional PLL circuit for intermittent operation. The terminal (2) is the switch circuit K for intermittent operation, +3) is the switch circuit (
2) a switch control circuit that controls ON/OFF of (4);
) is a reference signal oscillator, (5) is a fixed frequency divider for dividing the reference signal of reference signal oscillator (4), and (9) is a VCO (
Vohage Controlled 0scilla
tor), that is, a voltage controlled oscillator. (6) is a variable frequency divider for dividing the oscillation frequency generated by V CO (9), and (7) is a signal divided by the fixed frequency divider (5) and the variable frequency divider (6). (8) is a loop filter to convert the phase difference into voltage, and Ql is a loop filter (
8) is a capacitor for holding the voltage while the switch control circuit is OFF.

Next, we will explain the operation. ○This PLL circuit has V CO
The purpose is to stabilize (9). The signal generated by the reference signal oscillator (4) is frequency-divided by a fixed frequency divider (5), this frequency-divided signal is used as a reference signal, and this reference signal and the output signal of the variable frequency divider (6) are the same. If there is a phase difference between the output signal of the fixed frequency divider (5) and the output signal of the variable frequency divider (6), that phase difference is output from the phase comparator (7). and loop filter (8)
The phase difference is converted into voltage by , and the converted voltage is V
applied to CO(9). Due to this voltage fluctuation, V
The output frequency of the CO (9) changes and is input to the variable frequency divider (6), and this input signal is frequency-divided by the variable frequency divider (6) and input to the phase comparator (7). This operation is repeated until the signals of the fixed frequency divider (5) and phase comparator (7) are in the same phase.

Further, the circuit shown in FIG. 2 is a PLL circuit that performs intermittent operation in order to reduce power consumption. This intermittent operation is PL
The power consumption is reduced by turning off the power supplied to the L circuit for a certain period of time. 0N10F of this power supply
Control of F is performed by a switch control circuit (3). The above PLL operation is performed only when the switch circuit (2) is in the ON state, and the PLL does not operate when it is in the OFF state.

[Invention tries to solve! lI subject]

In a conventional PLL circuit, after the switch circuit is turned on, the reference signal oscillator and fixed frequency divider operate, and the output signal of the variable frequency divider is maintained until the reference signal output from the fixed frequency divider becomes stable. There is a problem in that the fixed frequency divider changes with the unstable reference signal output from the fixed frequency divider, and continues to operate unstable even after the output reference signal of the fixed frequency divider becomes constant.

This invention was made to solve the above problems, and its purpose is to prevent the PLL loop from the variable frequency divider to vCO from operating before the output reference signal of the fixed frequency divider becomes stable. do.

[Means to solve the problem]

The PLL circuit according to the present invention does not apply power to the variable frequency divider and phase comparator until the output reference signals of the reference signal oscillator and fixed frequency divider become stable, and
This is done so that the PLLA/- loop leading to this will not operate.

[Effect]

The PLL circuit according to the present invention can prevent unnecessary operations from the variable frequency divider to the VCO due to an unstable reference signal until the output signal of the fixed frequency divider becomes stable. As soon as the reference signal stabilizes, the variable frequency divider
PLL operations up to COf can be performed.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram of the PLL 1m path. In the figure, (
1) to αO are the same as those shown in the conventional example shown in FIG. 2, so their explanation will be omitted.

0]) are the reference signal oscillator (4) and the fixed frequency divider (5).
The voltage applied from the power supply voltage supply terminal (1) is applied to the variable frequency divider (6) and the phase comparator (7) until the voltage becomes stable and the output reference signal from the fixed frequency divider (5) becomes stable. This is a delay circuit to delay the

By inserting the delay circuit aυ, first the fixed frequency divider (
In order to perform the PLL operation of the variable frequency divider (6) or VCO (9) after the output reference signal of the fixed frequency divider (5) becomes stable, the variable frequency divider is used until the output reference signal of the fixed frequency divider (5) becomes stable. (
6) to v c O (9) can be prevented, and power consumption during this period can be reduced.

In addition, since there is no change in V CO (9) due to the unstable reference signal until the output reference signal of the fixed frequency divider (5) becomes stable, erroneous V CO (
9) The time required to correct the frequency can be saved.

〔Effect of the invention〕

As described above, according to the present invention, redundant operations of the PLL circuit can be omitted, and at the same time, the PLL loop can be brought into a stable state more quickly.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a PLL circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional PLL circuit. In the figure, % (1) is the power supply voltage supply terminal, (2) is the switch circuit, (3) is the switch control circuit, (4) is the reference signal oscillator, (5) is the fixed frequency divider, and (6) is the variable divider. peripheral organ,
(7) is a phase comparator, (8) is a loop filter, (9)
, VCOlQl is a capacitor, and 0υ is a delay circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In a PLL circuit consisting of a reference signal oscillator, a fixed frequency divider, a phase comparator, and a variable frequency divider, there is an A switch circuit for performing the operation, and a delay circuit between the power supply voltage terminals of the reference signal oscillator and fixed frequency divider of the switch circuit and the power supply voltage terminals of the phase comparator and variable frequency divider. Featured P
LL circuit.