JPH0377079A - Semiconductor inspecting device - Google Patents

Abstract

PURPOSE:To efficiently perform a test which a high speed by outputting two systems of timing signals in the same cycle, deciding by comparing the pattern of the signal with the pattern of an expected value and judging the quality of a device to be measured. CONSTITUTION:The inspecting device is constituted of a timing generator 3, a pattern generator 2 consisting of a pattern file 4 which outputs a timing pattern to the generator 3 in synchronism with the generator 3, a decision device 6 and a logical part 7. The two systems of timing signals A and B are inputted in the decision device 6 from the generator 3 in the same cycle, and a test pattern is transmitted to the device to be measured DUT 5 and an output from the device DUT 5 is inputted in the decision device 6. The decision device 6 respectively compares both patterns of the expected value from the file part 4 and the output from the DUT with the aid of the signals A and B and decides a propagation delay time, then the logical part 7 judges the quality of the DUT 5. Thus, a testing time is shortened, a testing process is simplified and a test program is facilitated, thereby efficiently performing the test with a high speed.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a semiconductor inspection apparatus that tests the propagation delay time of a device under test, and aims to speed up and improve the efficiency of AC testing of the device under test. In a semiconductor inspection apparatus that determines pass/fail based on the propagation delay time of the device under test using a pattern generator that applies voltage to the device and a determiner that compares and determines the output pattern of the device under test and the expected value pattern, The device includes a timing generator that outputs two systems of timing signals to the decision device within the same cycle, and a pattern file section that outputs a timing pattern to the timing generator and an expected value pattern to the decision device. The determining device is configured to include a logic section that determines whether the device under test is good or bad based on determination results based on two systems of timing signals from the timing generator.

[Industrial application field]

The present invention relates to a semiconductor testing device, and more particularly to a semiconductor testing device that tests the propagation delay time of a device under test.

Semiconductor inspection equipment has progressed as semiconductor devices become more highly integrated and faster. However, with the increase in integration and speed, A
The C (alternating current) test time, especially the propagation delay time test J11#, is increasing, and there is a demand for shortening the test time.

[Conventional technology]

Generally, as shown in FIG. 4, the output signal of a semiconductor device is delayed with respect to the input signal, and the quality of the semiconductor device (bus/
Fail> is decided. This propagation delay time tpd is determined, for example, between 50% of the rising edge of the input signal and the output signal, or between 50% of the falling edge of the input signal and the output signal.

Conventionally, propagation delay i and t of AC test using semiconductor inspection equipment
PD measurement is performed by applying a bus timing signal and a fail timing signal, which are timing signals (strobe signals), separately and independently in order to determine whether the device under test (semiconductor device, etc.) is bus/fail during a functional test. Generally, these results are combined to determine pass/fail.

Here, the relationship between input/output signals and strobe signals of the semiconductor device is shown in FIG. In FIGS. 5(A) to (D), the allowable propagation delay time tpd of the device under test is such that the rising edge of the output signal (FIG. 5(B)) is the input signal (FIG. 5(A)).
Fail timing signal (
MIN standard> and the longest bus timing signal (MAX
MA rating). Therefore, Fig. 5(B)
At the rising edge of the broken line of the output signal in the middle, the device under test is determined to be defective (Fail).The test is also performed at the falling edge of the input/output signal.

[Problem to be solved by the invention]

By the way, in the conventional semiconductor inspection apparatus, the type of determination of the output signal can only be expected to be either a bus expectation or a fail expectation. That is, when a mixture of fail-expecting timing signals and bus-expecting timing signals is applied, it is not possible to determine whether the rising edge (or falling edge) of the output signal is a fail-expecting signal or a bus-expecting signal. For this reason,
As shown in FIGS. 5(C) and (D), the MIN
After performing comparison timing with the standard fail timing signal to determine fail expectation, we perform comparison timing with the MAX standard bus timing signal to determine bus expectation, so the test must be conducted in two parts. I had to.

Therefore, since the test process is complicated, the test program becomes redundant and complicated, and the test time cannot be shortened.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a semiconductor testing device that increases the speed and efficiency of AC testing of semiconductor devices.

[Means to solve the problem]

FIG. 1 shows a diagram explaining the principle of the present invention.

In the semiconductor inspection apparatus 1 shown in FIG. 1, a pattern generator 2 includes a timing generator 3 and a pattern file section 4. As shown in FIG. Reference numeral 5 represents a device under test, and 6 represents a determiner, in which a logic section 7 is provided.

The timing generator 3 outputs two systems of timing signals A and B to the determiner 6 within the same cycle.

The pattern file unit 4 outputs the timing pattern to the timing generator 3 and also outputs the expected pattern to the determiner 6. In addition, the determiner 6 includes the device under test 5
The output pattern is compared and judged with the wealth value pattern from the pattern file section 4, and the logic section 7 judges whether the device under test is good or bad based on the judgment results based on the two systems of timing signals A and B from the timing generator 3. do.

[Function] The semiconductor inspection apparatus of the present invention inputs two systems of timing signals A and B to the determiner 6 in the same cycle, and uses these timing signals QA and B to detect the respective devices under test 5.
The propagation delay time is determined by comparing the output pattern and the expected value pattern.

Thereby, the logic unit 7 determines whether the device under test 5 is good or bad.

That is, based on the determination result of the output pattern of the device under test 5 according to the timing signal B and the determination result of the output pattern of the device under test 5 according to the timing signal B, the determination result of the output pattern of the device under test 5 according to the timing signal B is determined. It is a judgment of quality.

Therefore, since the test is processed at once, the test time is shortened, and the test program is simplified due to the simplification of the test process, thereby increasing the speed and efficiency of semiconductor testing.

〔Example〕

FIG. 2 shows a block diagram of an embodiment of the present invention.

The semiconductor inspection device 1 shown in FIG. 2 is used for AC testing. shows a functional test unit.

In FIG. 2, the pattern file section 4 of the pattern generator 2 is synchronized with the timing generator 3 by the Jl signal, and outputs a timing pattern to the timing generator 3. Further, the timing generator 3 outputs a test pattern to the device under test (hereinafter referred to as "DU-J") 5 via the driver 8, and in response to this, the DLIT 5 outputs an output pattern to the determiner 6. On the other hand, Timing generator 3 is 2
The stop 0-stop signals of the pass tying signal A and the fail timing signal B, which are system timing signals, are outputted to the determiner 6 within the same cycle. Then, the pattern file unit 4 outputs the expected value pattern to the determiner 6.

On the other hand, the determiner 6 receives the low level voltage ■o and high level voltage vo1 for output comparison. Further, the determination result of the bus timing signal A from the output terminal a of the determiner 6 is inputted to one input terminal of the AND circuit 7a of the logic section 7, and the determination result of the fail timing signal B is inputted to the output terminal of the inverter circuit 7b. The signal is inputted to the other input terminal of the AND circuit 8 via. Then, the AND circuit 7a outputs a pass/fail signal to the failure analysis memory (DFM>9).

Next, this operation will be explained with reference to the time chart of FIG. The OUT 5 receives an input signal of a test pattern from the timing generator 3 via the driver 8, and outputs an output pattern to the determiner 6 in response to this (FIG. 3(A),
(B)). The timing generator N3 outputs a strobe signal of fail timing signal B (MIN standard) to the determiner 6 after a certain period of time after outputting the test pattern.
From the timing pattern from pattern file section 4,
For example, the strobe signal of the bus timing signal A (MAX standard) created by etching the rising edge, etc., is sent to the determiner 6 at a predetermined time Iiii interval within the same cycle (OUT non-defective range).
(Figure 3 (C)). The pattern file unit 4 is synchronized with the timing generation B3 by a synchronization signal, and outputs each expected value pattern to the determiner 6 in synchronization with the bus timing signal A and fail timing signal B.

The determiner 6 compares the output logic of the DLJT 5 at the bus timing signal A and the fail timing (H@B) with the expected logic from the pattern file section 4.The output logic is determined when the output voltage is a low level voltage V.1 or less. If the voltage is higher than the high level voltage VOH, it is determined to be "H". This comparison is performed, for example, by determining whether the logic of the output waveform of OUT5 and the logic of the expected value pattern match at the above-mentioned timing.

The output terminal a of the determiner 6 outputs the determination result for the path timing signal @A to the AND circuit 7a of the logic section 7,
On the other hand, the output terminal Sukara outputs the determination result based on the fail timing signal B to the AND circuit 7a via the inverter circuit 7b. Then, the AND circuit 7a outputs the output (good or bad of the device under test 5) according to the input into the failure analysis memory (
DFM) 9, and all output signals are stored.

For example, the output terminals a and b of the determiner 6 output "H" when the output pattern of the DtJT5 and the holding pattern match. In other words, the expected value pattern is set to "H" because the bus is expected with the pass timing signal @A, and "L" is set because the fail timing signal B has fail rule.
” is set.

Therefore, the output pattern of DtJT5 is “H” when the bus is expected.
When this happens, the output terminal a becomes "H", and when the output pattern of the DLJT5 is "L", the output terminal a becomes "L".

In addition, the output pattern of DOT5 is “L” in case of fail hold.
When this happens, the output terminal becomes "H", and when the output pattern of DOT5 is "H", the output terminal becomes "L". Therefore, when the output terminal a is "H" as a result of the determination of the bus timing signal and the output terminal is "L" as a result of the determination of the fail timing signal B, the output of the AND circuit 7a is ” (solid line portion in FIG. 3 (8)), and the bus “H” signal is stored in the DFM 9. on the other hand,
Based on the judgment result of bus timing signal A, output terminal a is “
When the output is "L", the output of the AND circuit 7a becomes fail "L" regardless of the judgment result of the fail timing signal 8, and even if the output terminal a is #HN according to the judgment result of the pass timing signal @A. Depending on the judgment result of the fail timing signal B, the output terminal is “HIT” when the output terminal is “AND@”
The output of path 7a becomes "L" (failure) (broken line in FIG. 3(B)). This fail signal is sent to DFM9.
DOT 5 is stored in the memory, and the quality of the DOT5 is judged.

Incidentally, in the above embodiment, the case where the test was performed on the rising portion of the signal was shown, but the same applies to the falling portion.

In this way, two systems, the bus timing signal A and the fail timing signal B, are generated and output sequentially within the same cycle, and the quality of the OUT is judged based on the results of each judgment, so the test time is shorter than that of the conventional one. The test process is halved and the test process is simplified, so there is no need for a complicated test program.

〔Effect of the invention〕

As described above, according to the present invention, by comparing and determining two systems of timing signals within the same cycle, and determining the quality of DOT in accordance with each in the logic section, the test 111 hour cycle is significantly reduced. In addition to speeding up the process, it is also possible to simplify the test program and improve its efficiency.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a time chart in the embodiment, IF5 is a waveform diagram of the device under test, Fig. 5 is a time chart in a conventional semiconductor inspection device. In the figure, 1 is a semiconductor inspection device, 2 is a pattern generator, 3 is a timing generator, and 4 is a pattern 7? 5 is a device under test, 6 is a determiner, 7 is a logic section, 8 is a driver, and 9 is a failure analysis memory (DFM).

Claims (1)

[Claims] A pattern generator (2) that applies a test pattern to a device under test (5), a determiner (6) that compares and determines an output pattern of the device under test (5) and an expected value pattern. In the semiconductor inspection apparatus for determining pass/fail based on the propagation delay time of the device under test (5), the pattern generator (2) outputs two systems of timing signals to the determiner (6) within the same cycle. a timing generator (3) that outputs a timing pattern to the timing generator (3) and a pattern file section (4) that outputs an expected value pattern to the judger (6); (6) A semiconductor inspection apparatus characterized in that a logic section (7) is provided for determining whether the device under test (5) is good or bad based on determination results based on two systems of timing signals from the timing generator (3).