JPH0377287U - - Google Patents
Info
- Publication number
- JPH0377287U JPH0377287U JP13759489U JP13759489U JPH0377287U JP H0377287 U JPH0377287 U JP H0377287U JP 13759489 U JP13759489 U JP 13759489U JP 13759489 U JP13759489 U JP 13759489U JP H0377287 U JPH0377287 U JP H0377287U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- error signal
- voltage
- error
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 7
- 230000003321 amplification Effects 0.000 claims description 3
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 3
- 230000002265 prevention Effects 0.000 claims description 2
- 238000004804 winding Methods 0.000 claims 6
- 238000003079 width control Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Dc-Dc Converters (AREA)
Description
第１図は、本考案の一実施例を示す回路図、第
２図は従来装置の回路図である。
１０…スイツチング電源、２１…電流検出回路
、２２…誤差増幅回路、２３…ＰＷＭ制御回路、
２４…出力電圧低下防止回路。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional device. DESCRIPTION OF SYMBOLS 10... Switching power supply, 21... Current detection circuit, 22... Error amplification circuit, 23... PWM control circuit,
24...Output voltage drop prevention circuit.
Claims (1)
の一次巻線に印加される直流電圧をオンオフする
スイツチング素子Ｑと、このスイツチング素子の
オンオフにより当該二次巻線に誘起されるスイツ
チング信号を整流平滑化する二次側回路と、この
二次側回路の出力する電流に関連する電流検出信
号を出力する電流検出回路２１と、この二次側回
路の出力する電圧を第１の基準電圧と比較して誤
差信号を出力する誤差増幅回路２２と、当該電流
検出信号とこの誤差信号とを所定の比率で加算し
、この加算された電圧と第２の基準電圧とを比較
してこの差信号を小さくする方向に前記スイツチ
ング素子に制御信号を送るパルス幅制御回路２３
とを有するスイツチング電源を二台備え、各電源
の二次側回路出力端をダイオードを突合わせて並
列接続した直流安定化電源であつて、 各スイツチング電源に、前記二次側回路の出力
する電圧を第１の基準電圧と比較し、前記誤差増
幅回路の出力する誤差信号よりも大きな増幅率の
第２の誤差信号をダイオードを介して前記パルス
幅制御回路回路の電流検出信号と誤差信号とを所
定の比率で加算した信号に接続し、第２の誤差信
号が加算信号よりも大きいときは第２の誤差信号
が当該加算信号と絶縁され、第２の誤差信号が加
算信号よりも小さいときは第２の誤差信号が当該
加算信号と導通状態におかれ、この加算信号の値
を前記第２の基準電圧と等しい値にする出力電圧
低下防止回路２４を設け、 各スイツチング電源の誤差増幅回路の出力電圧
を連結して負荷電流を調整するロードシエア回路
を設けたことを特徴とする直流安定化電源の並列
運転制御装置。[Claims for Utility Model Registration] A transformer T having a primary winding and a secondary winding, a switching element Q that turns on and off the DC voltage applied to the primary winding, and a switching element Q that turns on and off the DC voltage applied to the primary winding, and a secondary winding that turns on and off the DC voltage applied to the primary winding. A secondary side circuit that rectifies and smoothes a switching signal induced in the line, a current detection circuit 21 that outputs a current detection signal related to the current output from this secondary side circuit, and a current detection circuit 21 that outputs a current detection signal related to the current output from this secondary side circuit. An error amplifier circuit 22 that compares the voltage with a first reference voltage and outputs an error signal, adds the current detection signal and this error signal at a predetermined ratio, and compares the added voltage with the second reference voltage. a pulse width control circuit 23 that sends a control signal to the switching element in a direction to reduce this difference signal by comparing the
A DC stabilized power supply comprising two switching power supplies having a secondary circuit output terminal of each power supply and connected in parallel with a diode, wherein each switching power supply has a voltage output from the secondary circuit. is compared with a first reference voltage, and a second error signal having a larger amplification factor than the error signal output from the error amplification circuit is connected to the current detection signal of the pulse width control circuit and the error signal via a diode. Connected to the signal added at a predetermined ratio, when the second error signal is larger than the addition signal, the second error signal is isolated from the addition signal, and when the second error signal is smaller than the addition signal, the second error signal is isolated from the addition signal. An output voltage drop prevention circuit 24 is provided in which a second error signal is brought into conduction with the addition signal to make the value of the addition signal equal to the second reference voltage. A parallel operation control device for a DC stabilized power supply, characterized by having a load sharing circuit that connects output voltages and adjusts load current.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989137594U JPH0750871Y2 (en) | 1989-11-28 | 1989-11-28 | Parallel operation controller for DC stabilized power supply |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989137594U JPH0750871Y2 (en) | 1989-11-28 | 1989-11-28 | Parallel operation controller for DC stabilized power supply |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0377287U true JPH0377287U (en) | 1991-08-02 |
| JPH0750871Y2 JPH0750871Y2 (en) | 1995-11-15 |
Family
ID=31684745
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989137594U Expired - Lifetime JPH0750871Y2 (en) | 1989-11-28 | 1989-11-28 | Parallel operation controller for DC stabilized power supply |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0750871Y2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006293943A (en) * | 2005-04-15 | 2006-10-26 | Canon Electronics Inc | Peripheral device card, host device, peripheral device card control method, peripheral device card control program, and host device control program |
| US7508946B2 (en) | 2001-06-27 | 2009-03-24 | Sony Corporation | Integrated circuit device, information processing apparatus, memory management method for information storage device, mobile terminal apparatus, semiconductor integrated circuit device, and communication method using mobile terminal apparatus |
-
1989
- 1989-11-28 JP JP1989137594U patent/JPH0750871Y2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7508946B2 (en) | 2001-06-27 | 2009-03-24 | Sony Corporation | Integrated circuit device, information processing apparatus, memory management method for information storage device, mobile terminal apparatus, semiconductor integrated circuit device, and communication method using mobile terminal apparatus |
| JP2006293943A (en) * | 2005-04-15 | 2006-10-26 | Canon Electronics Inc | Peripheral device card, host device, peripheral device card control method, peripheral device card control program, and host device control program |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0750871Y2 (en) | 1995-11-15 |
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