JPH0377712B2 - - Google Patents

Info

Publication number
JPH0377712B2
JPH0377712B2 JP57008176A JP817682A JPH0377712B2 JP H0377712 B2 JPH0377712 B2 JP H0377712B2 JP 57008176 A JP57008176 A JP 57008176A JP 817682 A JP817682 A JP 817682A JP H0377712 B2 JPH0377712 B2 JP H0377712B2
Authority
JP
Japan
Prior art keywords
region
photoelectric conversion
type
reverse bias
bias voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57008176A
Other languages
Japanese (ja)
Other versions
JPS58125961A (en
Inventor
Eiichi Takeuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP57008176A priority Critical patent/JPS58125961A/en
Publication of JPS58125961A publication Critical patent/JPS58125961A/en
Publication of JPH0377712B2 publication Critical patent/JPH0377712B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10FINORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10Integrated devices
    • H10F39/12Image sensors
    • H10F39/15Charge-coupled device [CCD] image sensors
    • H10F39/158Charge-coupled device [CCD] image sensors having arrangements for blooming suppression

Landscapes

  • Transforming Light Signals Into Electric Signals (AREA)

Description

【発明の詳細な説明】 本発明は電荷転送装置の駆動方法に関するもの
である。電荷転送装置を用いた撮像装置はフレー
ム転送方式、インターライン転送方式と呼ばれる
方式が開発されており、固体装置の特徴である小
型、低消費電力、高信頼性を柱に急速に発展して
いる。しかし撮像装置の利害得失を考えると、先
に述べた固体装置の利点の外、雑音、残像、焼き
付き、等では現在使用されている撮像管より優れ
ているがブルーミング、スミア現象に問題を残し
ている。またこの様な電荷転送装置をカメラ等の
システムとして用いる場合に入射光量を調節する
ため機械的機構、すなわち絞りを必要とする。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for driving a charge transfer device. Imaging devices using charge transfer devices have been developed using methods called frame transfer method and interline transfer method, and these devices are rapidly developing based on the characteristics of solid-state devices: compact size, low power consumption, and high reliability. . However, considering the advantages and disadvantages of imaging devices, in addition to the advantages of solid-state devices mentioned above, they are superior to currently used image pickup tubes in terms of noise, afterimages, burn-in, etc., but they still have problems with blooming and smearing. There is. Further, when such a charge transfer device is used as a system such as a camera, a mechanical mechanism, that is, an aperture is required to adjust the amount of incident light.

従来のインターライン転送方式による電荷転送
撮像装置は第1図に示すように同一電荷転送電極
群で駆動する複数列の垂直シフトレジスタ11
と、各垂直シフトレジスタの一側に隣接し、且つ
互いに電気的に分離された光電変換部12と、垂
直シフトレジスタと光電変換部の信号電荷転送を
制御するトランスフアゲート電極13と、各垂直
シフトレジスタの一端に電気的に結合した電荷転
送水平シフトレジスタ14と、水平シフトレジス
タの一端に信号電荷を検出する装置15が設けら
れている。
As shown in FIG. 1, a conventional charge transfer imaging device using an interline transfer method has multiple columns of vertical shift registers 11 driven by the same charge transfer electrode group.
, a photoelectric conversion unit 12 adjacent to one side of each vertical shift register and electrically isolated from each other, a transfer gate electrode 13 for controlling signal charge transfer between the vertical shift register and the photoelectric conversion unit, and each vertical shift register. A charge transfer horizontal shift register 14 is provided electrically coupled to one end of the register, and a signal charge sensing device 15 is provided at one end of the horizontal shift register.

このようなインターライン転送方式による電荷
転送撮像装置は、光電変換部12で入射光量に応
じて信号電荷を、例えばトランスフアゲート13
を介してそれぞれに対応する垂直シフトレジスタ
11へ転送する。垂直シフトレジスタへ信号電荷
を転送した後、トランスフアゲートが閉じられ、
光電変換部11は次の周期の信号電荷を蓄積す
る。一方垂直シフトレジスタ11へ転送された信
号電荷は並列に垂直方向に転送し、各垂直シフト
レジスタの一水平ライン毎に、水平シフトレジス
タ14に転送される。水平シフトレジスタへ送ら
れた電荷は次の垂直シフトレジスタから信号が転
送されて来る間に水平方向に信号電荷を転送し検
出する装置15から信号として外部に取り出され
る。
In a charge transfer imaging device using such an interline transfer method, a photoelectric conversion unit 12 converts a signal charge into a transfer gate 13 according to the amount of incident light.
The signals are transferred to the corresponding vertical shift registers 11 via the respective vertical shift registers 11. After transferring the signal charge to the vertical shift register, the transfer gate is closed,
The photoelectric conversion unit 11 accumulates signal charges for the next cycle. On the other hand, the signal charges transferred to the vertical shift register 11 are transferred vertically in parallel, and transferred to the horizontal shift register 14 for each horizontal line of each vertical shift register. The charge sent to the horizontal shift register is taken out as a signal from a device 15 that transfers and detects the signal charge in the horizontal direction while a signal is transferred from the next vertical shift register.

第2図は第1図に示す電荷転送撮像装置のA−
A′線上の断面を模式的に示したものである。第
2図において、基板半導体16とP−N接合を形
成し且つ、接合の深さが異なる二つのP型領域2
2,23が形成されており、及び接合の浅いP型
領域22上にはN型の光電変換領域24が形成さ
れており、接合の深いP型領域23上にはN型の
埋込みチヤネルの垂直シフトレジスタ25が形成
されている。
Figure 2 shows A- of the charge transfer imaging device shown in Figure 1.
This is a schematic diagram showing a cross section along line A'. In FIG. 2, there are two P-type regions 2 that form a P-N junction with the substrate semiconductor 16 and have different junction depths.
2 and 23 are formed, an N-type photoelectric conversion region 24 is formed on the P-type region 22 with a shallow junction, and a vertical N-type buried channel is formed on the P-type region 23 with a deep junction. A shift register 25 is formed.

第3図は第2図に光電変換部のB−B′線上の
電位分布図を示しており、横軸は深さ方向の距
離、縦軸は電位を表している。今第2図に示すチ
ヤネルストツプ領域20の電位を基準電位(この
場合0ボルト)とする。N型の光電変換領域24
はトランスフアゲート13の電圧をVTG、トラン
スフアゲートの閾値電圧をVTとするとVTG−VT
電位でセツトされる。またP型領域22と基板1
6に印加する直流の逆バイアス電圧VSUbを曲線2
6で示す低い電圧から、より高い逆バイアス電圧
VSUbにすると曲線27のようにP型領域22は完
全に空乏化する。光電変換領域24に光が照射さ
れ信号電荷が蓄積されると、光電変換領域24の
電位は曲線28から曲線29のように小さくなつ
てゆき最終的には曲線30のように光電変換領域
24とP型領域22の接合は順方向となり、これ
以上光電変換領域24で発生した電荷はP型領域
22を介して基板半導体16へ流れ込む。すなわ
ち第2図で示すトランスフアゲート13直下、チ
ヤネルストツプ領域20直下、および図示してい
ないが光電変換領域24を囲む全ての領域の表面
電位より光電変換領域24とP型領域22の接合
電位が高くなるように基板半導体とP型領域22
に直流の逆バイアス電圧を印加することにより、
光電変換領域24で発生する過剰電荷は完全に基
板半導体16へ掃き出すことができる。この構造
及び動作によつてブルーミング現象を完全に抑制
することができる。
FIG. 3 shows a potential distribution diagram on line B-B' of the photoelectric conversion section in FIG. 2, where the horizontal axis represents the distance in the depth direction and the vertical axis represents the potential. Let us now assume that the potential of the channel stop region 20 shown in FIG. 2 is a reference potential (in this case, 0 volts). N-type photoelectric conversion region 24
is set at a potential of V TG -V T, where the voltage of the transfer gate 13 is V TG and the threshold voltage of the transfer gate is V T. In addition, the P-type region 22 and the substrate 1
The direct current reverse bias voltage V SUb applied to curve 2
From the lower voltage shown at 6 to the higher reverse bias voltage
When VSUb is set, the P-type region 22 is completely depleted as shown by a curve 27. When the photoelectric conversion region 24 is irradiated with light and signal charges are accumulated, the potential of the photoelectric conversion region 24 decreases from the curve 28 to the curve 29, and finally the potential of the photoelectric conversion region 24 decreases as shown by the curve 30. The junction of the P-type region 22 is in the forward direction, and any more charges generated in the photoelectric conversion region 24 flow into the substrate semiconductor 16 via the P-type region 22. In other words, the junction potential between the photoelectric conversion region 24 and the P-type region 22 is higher than the surface potential of the areas directly below the transfer gate 13, directly below the channel stop region 20, and all regions (not shown) surrounding the photoelectric conversion region 24 shown in FIG. The substrate semiconductor and the P-type region 22
By applying a DC reverse bias voltage to
Excess charges generated in the photoelectric conversion region 24 can be completely swept out to the substrate semiconductor 16. With this structure and operation, the blooming phenomenon can be completely suppressed.

しかしこの様な電荷転送撮像装置をカメラ等の
システムとして用いる場合に入射光量を機械的機
構、すなわち絞りによつて調節しなければならな
い欠点があつた。
However, when such a charge transfer imaging device is used as a system such as a camera, there is a drawback that the amount of incident light must be adjusted by a mechanical mechanism, that is, an aperture.

本発明の目的は上記の欠点を無くし、前記のブ
ルーミング抑制可能な電荷転送装置の新しい駆動
方法を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide a new method for driving a charge transfer device capable of suppressing the blooming described above.

本発明によれば、半導体基板の主面に、前記基
板と反対の導電型を形成してなる接合領域で、前
記接合深さが浅い第1の領域と、前記接合深さが
深い第2の領域を設け、前記第1の領域の主面に
光電変換素子群を形成し、前記第2の領域の主面
に前記光電変換素子群からの信号を読み出す装置
を形成してなる電荷転送撮像装置において、1フ
イールドの期間中に前記第1の領域と光電変換素
子群とが順方向となるように通常の逆バイアス電
圧より高い電圧を前記第1の領域及び第2の領域
と前記半導体基板間に印加して、一定期間の後前
記第1の領域が完全に空乏化するのに必要な通常
の逆バイアス電圧を前記第1の領域及び第2の領
域と前記半導体基板に印加することを特徴とする
電荷転送撮像装置の駆動方法が得られる。
According to the present invention, in the junction region formed on the principal surface of a semiconductor substrate and having a conductivity type opposite to that of the substrate, the first region has a shallow junction depth and the second region has a deep junction depth. A charge transfer imaging device comprising a region, a group of photoelectric conversion elements is formed on the main surface of the first region, and a device for reading out signals from the group of photoelectric conversion elements is formed on the main surface of the second region. In this step, a voltage higher than a normal reverse bias voltage is applied between the first region and the second region and the semiconductor substrate so that the first region and the photoelectric conversion element group are in the forward direction during one field period. and applying a normal reverse bias voltage necessary for the first region to be completely depleted after a certain period of time to the first region, the second region, and the semiconductor substrate. A method for driving a charge transfer imaging device is obtained.

次に本発明の実施例について図面を用いて説明
する。以後本発明の実施例については説明を簡単
にするためNチヤンネルの半導体装置について述
べることにする。
Next, embodiments of the present invention will be described using the drawings. Hereinafter, in the embodiments of the present invention, an N-channel semiconductor device will be described to simplify the explanation.

第4図は本発明の一実施例を説明するための駆
動パルス波形図である。従来例と違いは、第2図
に示した半導体基板とP−N接合を形成し且つ接
合深さが異なる二つのP型領域22,23との間
に印加する逆バイアス電圧subが二つのレベル
“Vs”、“Vp”を持つことである。
FIG. 4 is a drive pulse waveform diagram for explaining one embodiment of the present invention. The difference from the conventional example is that the reverse bias voltage sub applied between the semiconductor substrate and the two P-type regions 22 and 23 that form a P-N junction and have different junction depths as shown in FIG. 2 has two levels. It means having “V s ” and “V p ”.

第5図は第3図と同様に、第2図に示す電荷転
送撮像装置のB−B′線上の深さ方向の電位を示
したものである。
Similar to FIG. 3, FIG. 5 shows the potential in the depth direction on the line B-B' of the charge transfer imaging device shown in FIG.

第4図における時刻t1のとき、基板半導体16
とP−N接合を形成するP型領域22との間に印
加する逆バイアス電圧subは“Vp”である。第5
図において、この逆バイアス電圧sub“Vp”はN
型の光電変換領域24とP型領域22との間が順
方向となる必要がある。第5図にこの逆バイアス
電圧sub“Vp”の作る電位分布の曲線を31で示
す。この逆バイアス電圧sub“Vp”のレベルの期
間、光電変換領域24に入射して発生した電荷
は、N型の光電変換領域24とP型領域22が順
方向となつているため基板半導体16に掃き出さ
れるため、信号電荷とはならない。
At time t 1 in FIG. 4, the substrate semiconductor 16
The reverse bias voltage sub applied between the P-type region 22 and the P-type region 22 forming the P-N junction is "V p ". Fifth
In the figure, this reverse bias voltage sub “V p ” is N
The direction between the photoelectric conversion region 24 of the mold and the P-type region 22 must be in the forward direction. In FIG. 5, the potential distribution curve created by this reverse bias voltage sub "V p " is shown at 31. During the period when the reverse bias voltage sub "V p " is at the level, the charges generated by entering the photoelectric conversion region 24 are transferred to the substrate semiconductor 16 because the N-type photoelectric conversion region 24 and the P-type region 22 are in the forward direction. It does not become a signal charge because it is swept out.

時刻t2のとき、逆バイアス電圧subは“Vp”か
ら“Vs”に変るため、光電変換部の深さ方向電
位を示す曲線は31から曲線27に変る。逆バイ
アス電圧subが“Vs”のレベル期間中、N型の光
電変換領域24に入射した光によつて発生した電
荷は信号電荷となり、N型の光電変換領域24に
蓄積され、入射光量に応じてN型の光電変換領域
24の電位は曲線28から小さくなつていく。
At time t 2 , the reverse bias voltage sub changes from “V p ” to “V s ”, so the curve indicating the depth direction potential of the photoelectric conversion section changes from 31 to curve 27 . During the period when the reverse bias voltage sub is at the level of “V s ”, charges generated by light incident on the N-type photoelectric conversion region 24 become signal charges, are accumulated in the N-type photoelectric conversion region 24, and the amount of incident light changes. Correspondingly, the potential of the N-type photoelectric conversion region 24 decreases from the curve 28.

時刻t3のとき、トランスフアゲートに電圧圧
VTGが印加され、N型の光電変換領域24に蓄積
されていた信号電荷は垂直シフトレジスタ11に
転送される。この時、N型の光電変換領域24は
VTG−VTの電位でセツトされる。
At time t 3 , the voltage at the transfer gate is
V TG is applied, and the signal charges accumulated in the N-type photoelectric conversion region 24 are transferred to the vertical shift register 11 . At this time, the N-type photoelectric conversion region 24 is
It is set at a potential of V TG - VT .

垂直シフトレジスタが電荷転送を始める前の時
刻t4のとき、N型の光電変換領域24は再び逆バ
イアス電圧Vsub“Vp”が印加され、次のフイー
ルドの動作を繰り返していく。
At time t4 , before the vertical shift register starts charge transfer, the reverse bias voltage Vsub " Vp " is again applied to the N-type photoelectric conversion region 24, and the operation of the next field is repeated.

この動作により1フイールドでの光の蓄積時間
は時刻t2から時刻t3までの期間T1である。期間T1
を入射光量に応じ、入射光量が多い時は短く、入
射光量が少い時は長くして信号電荷量を制御でき
る。この為従来カメラ等で使用していた絞りの機
構は不用となる。
Due to this operation, the light accumulation time in one field is a period T1 from time t2 to time t3 . Period T 1
The amount of signal charge can be controlled by making it short when the amount of incident light is large and lengthening it when the amount of incident light is small depending on the amount of incident light. Therefore, the diaphragm mechanism used in conventional cameras and the like is no longer necessary.

また逆バイアス電圧sub“Vp”は“Vs”より大
きくN型の光電変換領域とP型領域22と間を順
方向にする電圧以上あれば良いが、垂直シフトレ
ジスタ直下のP型領域25を空乏化するまでの大
きな電圧にしてはならない。
Further, the reverse bias voltage sub "V p " needs to be greater than "V s " and at least a voltage that makes the connection between the N-type photoelectric conversion region and the P-type region 22 in the forward direction. Do not apply a voltage high enough to deplete the capacitor.

以上本発明の実施例についてその駆動法をNチ
ヤネルについて説明したが各領域の導電型を反対
にすることでPチヤネル半導体装置に適用できる
ことは言うまでもない。
Although the driving method of the embodiment of the present invention has been described above for an N-channel, it goes without saying that it can be applied to a P-channel semiconductor device by reversing the conductivity type of each region.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の電荷転送装置を用いた撮像装置
の平面図、第2図は第1図に示すA−A′線上の
断面模式図に、第3図は第2図に示すB−B′線
上の電位分布を示している。第4図は本発明の実
施例を説明するための駆動パルス波形、第5図は
本発明の駆動法による第2図に示すB−B′線上
の電位分布を示している。 図において、11……垂直シフトレジスタ、1
2……光電変換部、13……トランスフアゲー
ト、14……水平シフトレジスタ、15……電荷
検出装置、16……半導体基板、17……絶縁
膜、18……垂直シフトレジスタ電極、19……
トランスフアゲート電極、20……チヤンネルス
トツプパー、21……光遮蔽、22,23……P
型領域、24……N型の光電変換領域、25……
N型の垂直シフトレジスタ、26,27,28,
29,30,31……電位分布を示す曲線、であ
る。
Fig. 1 is a plan view of an imaging device using a conventional charge transfer device, Fig. 2 is a schematic cross-sectional view taken along line A-A' shown in Fig. 1, and Fig. 3 is a schematic cross-sectional view taken along line B-B shown in Fig. 2. ’ shows the potential distribution on the line. FIG. 4 shows a driving pulse waveform for explaining an embodiment of the present invention, and FIG. 5 shows a potential distribution on the line B-B' shown in FIG. 2 according to the driving method of the present invention. In the figure, 11...vertical shift register, 1
2... Photoelectric conversion unit, 13... Transfer gate, 14... Horizontal shift register, 15... Charge detection device, 16... Semiconductor substrate, 17... Insulating film, 18... Vertical shift register electrode, 19...
Transfer gate electrode, 20...channel stopper, 21...light shielding, 22, 23...P
Type region, 24... N-type photoelectric conversion region, 25...
N-type vertical shift register, 26, 27, 28,
29, 30, 31...Curves showing potential distribution.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板の主面に、前記基板と反対の導電
型を形成してなる接合領域で、前記接合深さが浅
い第1の領域と、前記接合深さが深い第2の領域
を設け、前記第1の領域の主面に光電変換素子群
を形成し、前記第2の領域の主面に前記光電変換
素子群からの信号を読み出す装置を形成してなる
電荷転送撮像装置において、1フイールドの期間
中に前記第1の領域と光電変換素子群とが順方向
となるように通常の逆バイアス電圧より高い電圧
を前記第1の領域及び第2の領域と前記半導体基
板間に印加して、一定期間の後前記第1の領域が
完全に空乏化するのに必要な通常の逆バイアス電
圧を前記第1の領域及び第2の領域と前記半導体
基板に印加することを特徴とする電荷転送撮像装
置の駆動方法。
1. A first region having a shallow junction depth and a second region having a deep junction depth are provided on a main surface of a semiconductor substrate, the junction region having a conductivity type opposite to that of the substrate, and the second region having a shallow junction depth. In a charge transfer imaging device, a group of photoelectric conversion elements is formed on the main surface of the first region, and a device for reading out signals from the group of photoelectric conversion elements is formed on the main surface of the second region. Applying a voltage higher than a normal reverse bias voltage between the first region and the second region and the semiconductor substrate so that the first region and the photoelectric conversion element group are in the forward direction during the period, Charge transfer imaging characterized in that a normal reverse bias voltage necessary for the first region to be completely depleted after a certain period of time is applied to the first region, the second region, and the semiconductor substrate. How to drive the device.
JP57008176A 1982-01-21 1982-01-21 Driving method for charge transfer imaging device Granted JPS58125961A (en)

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JP57008176A JPS58125961A (en) 1982-01-21 1982-01-21 Driving method for charge transfer imaging device

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Application Number Priority Date Filing Date Title
JP57008176A JPS58125961A (en) 1982-01-21 1982-01-21 Driving method for charge transfer imaging device

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JPS58125961A JPS58125961A (en) 1983-07-27
JPH0377712B2 true JPH0377712B2 (en) 1991-12-11

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Publication number Priority date Publication date Assignee Title
JP2517882B2 (en) * 1986-12-23 1996-07-24 ソニー株式会社 Solid-state imaging device
JP2605294B2 (en) * 1987-08-14 1997-04-30 ソニー株式会社 Solid-state imaging device
JP2565247B2 (en) * 1995-04-21 1996-12-18 ソニー株式会社 Exposure time control method for solid-state imaging device and video camera

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JPS58125961A (en) 1983-07-27

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