JPH0378190A - Dynamic ram - Google Patents

Abstract

PURPOSE:To maintain the potential of a memory cell at a source voltage even when loss occurs in the parasitic coupling capacity of a word line and a bit line by boosting the potential of the bit line over the source voltage when performing write. CONSTITUTION:When the rewrite of High data on the memory cell is performed, the potential of an Ni is set at the source voltage by falling an So' signal provided newly before the word line falls, and the potential of the bit line BL is boosted over the source voltage by the coupling of a capacity 12. Also, the value of boosting (boosted voltage - source voltage) can be set at the one equivalent to the loss of potential due to the parasitic coupling capacity 100 of the word line WL and the bit line BL. In such a way, the potential of the memory cell can be charged to the source voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sense amplifier for a dynamic RAM.

[Conventional technology]

FIG. 3 is a circuit diagram of a conventional sense amplifier, which includes p-channel transistors fl), (2), (3) and n-channel transistors f4J, f5), (
The sense amplifier is configured by 6). The part surrounded by a dotted line is a memory cell (MC), which is composed of an n-channel transistor (101) and a camber (102), and Vmc is 0 or W, which indicates the potential of the node shown in the figure.
L is the word line, So, So is the word line W
BL is a sense amplifier drive signal generated in response to a change in the L signal.

The numeral indicates the focus line pair, and the capacitance (100) indicates the coupling capacitance parasitically created between ML and BE. Figure 4 shows the timing chart of each signal, and VBL is in focus! BL.

is the potential of

Next, a description will be given of the operation of reading high data from a memory cell and rewriting (refreshing) high data to the memory cell accordingly.

First, connect the pinto line pair to -Vcc (Vcc; power supply voltage)
to start up the word line of the memory cell.

When VBL = -Vcc and So rises in response to a change in word line potential, the n-channel transistor (6) turns on and the gate-source voltage of the n-channel transistor (5) becomes higher than the gate dark potential Vπh. The n-channel transistor (5) turns on before the n-channel transistor (4). As a result, the anal potential is discharged to Ov. The potential of BE is about to be discharged due to the instantaneous ON operation of the transistor (4), but the cutoff of the n-channel transistor (4) due to the voltage becoming Ov, and the cut-off of the p-channel transistor ( 11 and +21 are finally charged to the power supply voltage.

In this way, high reading from the memory cell is performed.Then, rewriting (refreshing) is performed automatically by lowering the milk.
When WL falls, the potential VBL of the bit line drops below the power supply voltage due to the parasitic coupling capacitance of WL and BL, and the voltage of the memory cell also drops accordingly, resulting in a loss of margin.

[Problem to be solved by the invention]

Conventional sense amplifiers are configured as described above, so when writing high data or rewriting, word edges,
There is a problem in that the potential of the memory cell drops below the power supply voltage due to the parasitic coupling capacitance of the hint, resulting in loss of margin.

This invention was made to eliminate the above-mentioned problem, and aims to bring the potential of a memory cell to the power supply voltage.

[Means to solve the problem]

The dynamic RAM sense amplifier according to the present invention includes:
A circuit is added to boost the potential of the focus line by f more than the power supply voltage when rewriting (refreshing) high data to the memory cell and writing high data.

[Effect]

The sense amplifier of the dynamic RAM in this invention does not raise the potential of the bit line above the power supply voltage during writing, and increases the potential of the memory cell to the power supply voltage even if there is loss due to parasitic coupling capacitance between the word line and the bit line. to be maintained.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a sense amplifier which is an embodiment of the present invention. In addition to the conventional sense amplifier circuit shown in FIG. 0◇, a capacitor (2) is provided for boosting the voltage. FIG. 2 is a timing chart of each signal when the sense amplifier shown in FIG. 1 operates.

High from 0 memory cell whose operation will be explained next.
Data reading is exactly the same as the conventional method. In this embodiment, when rewriting high data to the memory cell, the newly provided 80' signal is brought down before the word line is brought down, so that the N
The idea is to use the + potential as the power supply voltage and to boost the potential of the pinto line BTA to a level higher than the power supply voltage by compres- ing the proverbial capacitor O.

This boosted voltage (boosted potential - power supply voltage) is the word line WL,
The potential loss due to the parasitic coupling capacitance of the bit green BL suffices,
As a result, the potential of the memory cell is photoelectrically adjusted to the power supply voltage.

Note that when the data of a memory cell is low, the cell becomes high.
A similar explanation can be given to the case where gh data is written.

〔Effect of the invention〕

As described above, according to the present invention, Hi
gh data rewrite (refresh) and High
When writing data, the potential of the pinto line is boosted above the power supply voltage, so even if there is potential loss due to parasitic coupling capacitance between the word line and bit line when the word line falls, the memory cell potential is charged to the power supply voltage. be done. Since the potential of the memory cell is charged just to the power supply voltage, this has the effect of increasing the amount of charge stored in the cell and speeding up the access time of the dynamic RAM.

[Brief explanation of drawings]

FIG. 1 shows a dynamic RAM according to an embodiment of the present invention.
Sense amplifier circuit diagram, Figure 2 is a timing chart of each signal in Figure 1, Figure 3 is a circuit diagram of a conventional dynamic RAM sense amplifier, Figure 4 is a timing chart of each signal in Figure 83. In a certain diagram, (1), +2>, +31. Ql is a p-channel transistor (4
1, (51, ((3)0υ is n that constitutes the sense amplifier)
(10t) is the n-channel transistor that makes up the memory cell, (102) is the storage capacitor that makes up the memory cell, (100) is between the word line and the bit line. Figure 1 shows the parasitic coupling capacitance of 0. In the figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] High data rewriting to memory cells and High
A dynamic RAM characterized by boosting the potential of a bit line to a level higher than the power supply voltage when writing data.