JPH0380552A - Tape for mounting integrated circuit - Google Patents

Tape for mounting integrated circuit

Info

Publication number
JPH0380552A
JPH0380552A JP1217928A JP21792889A JPH0380552A JP H0380552 A JPH0380552 A JP H0380552A JP 1217928 A JP1217928 A JP 1217928A JP 21792889 A JP21792889 A JP 21792889A JP H0380552 A JPH0380552 A JP H0380552A
Authority
JP
Japan
Prior art keywords
lead
lead frame
tape
integrated circuit
heat dissipating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1217928A
Other languages
Japanese (ja)
Inventor
Yuji Iwata
岩田 勇治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1217928A priority Critical patent/JPH0380552A/en
Publication of JPH0380552A publication Critical patent/JPH0380552A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/726Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To improve heat dissipation, reduce the irregularity of pitch of an outer lead part, and realize superior outer lead bonding, by forming a heat dissipating part on the peripheral surface in the vicinity of a lead frame and a device hole. CONSTITUTION:Bumps 2 to be connected with lead frames 3 are formed on the outer periphery of the surface of an LSI chip 1. On the other hand, by well-known exposure and etching technique of a copper foil, lead frames 3 having an inner lead part B1 and an outer lead part B0, a device hole 5, a heat dissipating part 4, and sprocket holes 6 are formed. Then by performing a specified gold-plating, a tape for mounting an LSI chip is formed. The heat dissipating part 4 is formed so as to have a thickness T larger than the thickness (t) of the lead frame 3, in order to increase heat dissipating effect. As the result, the heat supplied from a bonding tool 10 in the course of bonding diffuses in the heat dissipating part formed on the periphery of the device holes 5, via the lead frames 3, and the temperature rise in the lead frames 3 and on the tape surface can be remarkably restratined, so that extension and deformation of the lead frames 3 can be reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、TAB (Tape Automated 
Bonding)方式による集積回路実装用テープに関
し、特に超多端子、狭リード幅を必要とする集積回路実
装用テープの構造に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to a TAB (Tape Automated
The present invention relates to an integrated circuit mounting tape using the bonding method, and particularly to the structure of an integrated circuit mounting tape that requires a large number of terminals and a narrow lead width.

〔従来の技術〕[Conventional technology]

従来、超多ビン、狭リード幅を必要とするこの種の端子
接続は、大規模集積回路チップ(以下LSIチップと略
記する)の周縁部にバンプを形成し、ポリイミドフィル
ム上のデバイスホール内に形成されたリードフレームと
、当該バンプを接続するTAB技術により行なわれてい
た。すなわち第6図及び第7図に示す構造となっていた
。このようにデバイスホール5とスプロケットホール6
とが設けられたポリイミドフィルム7に所定の本数のリ
ードフレーム3部と、放熱部4を有するメツキ配線9が
接着剤8により固定されている。
Conventionally, this type of terminal connection, which requires a very large number of pins and a narrow lead width, is performed by forming bumps on the periphery of a large-scale integrated circuit chip (hereinafter abbreviated as LSI chip) and placing bumps in device holes on a polyimide film. The TAB technique was used to connect the formed lead frame and the bump. That is, the structure was as shown in FIGS. 6 and 7. In this way, device hole 5 and sprocket hole 6
A predetermined number of lead frames 3 and a plating wiring 9 having a heat dissipating section 4 are fixed to a polyimide film 7 provided with an adhesive 8.

B、をLSIチップ1のバンプ2にボンディングする。B is bonded to the bump 2 of the LSI chip 1.

上述した従来の超多端子、狭す−ド幅を必要とする集積
回路装置のテープ構造では、ポリイミドフィルム7と密
着している金属部分は、リードフレーム3とそれに接続
されているメツキ配線9のみであるため、ボンディング
時のボンディングツール10から伝達される熱の放散が
悪く、温度が下がらない為、リードフレーム3の伸び、
ポリイミドフィルム7とリードフレーム3及びメツキ配
線9の接着部分8での剥れ、ポリイミドフィルム7の変
形及び収縮を起こしてしまうという欠点がある。
In the conventional tape structure of an integrated circuit device that requires a large number of terminals and a narrow lead width, the only metal parts that are in close contact with the polyimide film 7 are the lead frame 3 and the plated wiring 9 connected thereto. Therefore, the heat transmitted from the bonding tool 10 during bonding is poorly dissipated and the temperature does not drop, causing the lead frame 3 to elongate,
There are disadvantages in that the polyimide film 7 and the lead frame 3 and the plating wiring 9 are peeled off at the adhesive portion 8, and the polyimide film 7 is deformed and shrunk.

その結果、リード相互間のリードピッチPの不揃いを起
こし、リードフレーム3のインナーリード部B1とバン
プ2との接続の後、リードフレーり離し、アウターリー
ドボンディングを行う場合にこのピッチPの不揃いによ
り、ボンディングが正常に行なえないという欠点がある
As a result, the lead pitch P between the leads becomes uneven, and after the inner lead portion B1 of the lead frame 3 and the bump 2 are connected, when the lead flakes are separated and outer lead bonding is performed, the unevenness of the pitch P causes However, there is a drawback that bonding cannot be performed normally.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

本発明の目的は、リードフレームのインナーリード部と
LSIチップのバンプとのボンディングの際、加わる熱
の放散を良好にし、アウターリード部のピッチの不揃い
を緩和し、良好なアウターリードボンディングが行なえ
る集積回路実装用テープを提供することにある。
An object of the present invention is to improve the dissipation of heat applied during bonding between the inner lead portion of a lead frame and the bump of an LSI chip, to alleviate uneven pitch of the outer lead portion, and to perform good outer lead bonding. An object of the present invention is to provide a tape for mounting integrated circuits.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の集積回路装置のテープ構造は、リードフレーム
とデバイスホールの外側とが同一金属材料から成り、デ
バイスホール近傍の周囲にリードフレームのリード厚t
よりも厚い(寸法T)放熱部を有している。このような
構成により、LSIチップとリードフレームとのボンデ
ィングの際に加わる熱は表面積を大きく形成した放熱部
はもとより放熱部の外側のテープ部金属からも放散され
るため、より効率的な放熱を行なうことができる。
In the tape structure of the integrated circuit device of the present invention, the lead frame and the outside of the device hole are made of the same metal material, and the lead frame has a lead thickness t around the vicinity of the device hole.
It has a heat dissipation part that is thicker (dimension T). With this configuration, the heat applied during bonding between the LSI chip and the lead frame is dissipated not only from the heat dissipation section, which has a large surface area, but also from the metal tape outside the heat dissipation section, resulting in more efficient heat dissipation. can be done.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は、本発明の第1の実施例を示す平面図であり、
第2図は第1図のA−A’線断面図である。L S、 
Iデフ11表面の外縁部にはリードフレーム3との接続
を行なうバンプ2が形成されている。一方、銅箔を周知
の露光とエツチング技術によりインナーリード部B!及
びアウターリード部B。を有するリードフレーム3とデ
バイスホール5と放熱部4とスプロケットホール6を形
成した後、所定の金メツキ(又はスズメツキ)を施して
LSIチップ実装用テープが形成されている。
FIG. 1 is a plan view showing a first embodiment of the present invention,
FIG. 2 is a sectional view taken along the line AA' in FIG. 1. L.S.
A bump 2 is formed on the outer edge of the surface of the I-differential 11 for connection to a lead frame 3. On the other hand, the inner lead part B is formed using well-known exposure and etching techniques on the copper foil. and outer lead part B. After forming a lead frame 3, a device hole 5, a heat radiation section 4, and a sprocket hole 6, a predetermined gold plating (or tin plating) is applied to form an LSI chip mounting tape.

ここで放熱部4は放熱効果を高めるためリードフレーム
3の肉厚tに比べ厚い寸法Tになるように形成されてい
る。
Here, the heat dissipation portion 4 is formed to have a dimension T thicker than the wall thickness t of the lead frame 3 in order to enhance the heat dissipation effect.

次に第3図(a)〜(c)を参照してLSIチップ1と
リードフレーム3とのボンディングについて説明する。
Next, bonding between the LSI chip 1 and the lead frame 3 will be described with reference to FIGS. 3(a) to 3(c).

第3図(a)のようにLSIチップ1のバンプ2とLS
Iチップ実装用テープのリードフレーム3とを1対1の
インナーリード部B、に目合わせして両者をボンディン
グツール10により第3図(b)のように同時に加熱圧
着してインナーリード部B、をボンディングする。ここ
で実装用テープのデバイスホール5近傍に放熱部4を形
成しているので第3図(C)に示すようにボンディング
中にボンディングツール10から供給される熱は、リー
ドフレーム3を通してデバイスホール5の周囲に形成さ
れた放熱部4に拡がり、その表面より放熱することが可
能となる。そのため、リードフレーム3及びテープ表面
での温度上昇を大幅におさえられるので、リードフレー
ム3の伸び及び変形を緩和することができる。また、本
発明のLSIチップ実装用テープは全体が銅箔に金メツ
キを施したものであるので、従来のようにボンディング
時に加わる熱によってポリイミドフィルムからはがれる
事がなく、放熱部4より外側のテープ部からも放熱され
るためピッチの不揃いやリードフレーム3部の切り離し
の際の変形も防止することができる。
As shown in Figure 3(a), bump 2 of LSI chip 1 and LS
The lead frame 3 of the I-chip mounting tape is aligned one-to-one with the inner lead part B, and both are simultaneously heated and pressed together using the bonding tool 10 as shown in FIG. 3(b) to form the inner lead part B. Bonding. Since the heat dissipation part 4 is formed near the device hole 5 of the mounting tape, the heat supplied from the bonding tool 10 during bonding is transmitted through the lead frame 3 to the device hole 5 as shown in FIG. 3(C). It spreads to the heat dissipation part 4 formed around the , and it becomes possible to dissipate heat from the surface. Therefore, the temperature rise on the lead frame 3 and the tape surface can be significantly suppressed, so that the elongation and deformation of the lead frame 3 can be alleviated. In addition, since the LSI chip mounting tape of the present invention is entirely made of copper foil plated with gold, it does not peel off from the polyimide film due to the heat applied during bonding, unlike conventional tapes outside the heat dissipation section 4. Since heat is also radiated from the lead frame, irregular pitches and deformation when the three parts of the lead frame are separated can be prevented.

第4図は本発明の第2の実施例の平面図であり、第5図
はB−B’線断面図である。本実施例では、デバイスホ
ール5を取り囲むように形成された放熱部4がリードフ
レーム3の厚さtより厚い寸法Tの複数の凸状として設
けられている。そのため第1図及び第2図に示した第1
の実施例よりも放熱面積を増すことが出きるのでさらに
放熱特性が優れているという利点がある。
FIG. 4 is a plan view of a second embodiment of the present invention, and FIG. 5 is a sectional view taken along the line BB'. In this embodiment, the heat dissipation portion 4 formed to surround the device hole 5 is provided as a plurality of convex shapes having a dimension T thicker than the thickness t of the lead frame 3. Therefore, the first
Since the heat dissipation area can be increased compared to the embodiment described above, there is an advantage that the heat dissipation characteristics are even better.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は同一金属材料から構成され
たLSIチップ実装用テープにおいて、リードフレーム
3とデバイスホール近傍の周囲に放熱部4を形成するこ
とにより、インナーリードボンディング時のボンディン
グツールIOからの熱は、放熱部4及び放熱部4の外側
のテープ部から十分に放熱できるのでリードフレーム3
の伸び及び変形が防止でき、リード相互間のリード間ピ
ッチPを確保できる効果がある。結果的に、アウターリ
ードボンディングが正常に行なえるという効果がある。
As explained above, the present invention provides an LSI chip mounting tape made of the same metal material, by forming a heat dissipation part 4 around the lead frame 3 and the vicinity of the device hole, so that the bonding tool IO during inner lead bonding can be easily removed. Since the heat can be sufficiently radiated from the heat dissipation section 4 and the tape section outside the heat dissipation section 4, the lead frame 3
Elongation and deformation of the leads can be prevented, and the pitch P between the leads can be ensured. As a result, there is an effect that outer lead bonding can be performed normally.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の第1の実施例を説明するための集積回
路実装用テープの平面図、第2図は第1図のA−A’線
断面図、第3図(a)〜(c)はTAB法によるLSI
チップを本発明の集積回路実装用テープへの組み立てを
説明するための工程断面図、第4図は本発明の第2の実
施例を説明するための平面図、第5図は第4図のB−B
’線断面図、第6図は従来技術による平面図、第7図は
第6図のC−C’線断面図である。 1・・・・・・LSIチップ、2・・・・・・バンプ、
3・・・・・・リードフレーム、4・・・・・・放熱部
、5・・・・・・デバイスホール、6・・・・・・スプ
ロケットホール、7・・・・・・ポリイミドフィルム、
8・・・・・・接着剤、9・・・・・・メツキ配線、1
0・・・・・・ボンディングツール、P・・・・・・リ
ード間ピッチ%BI・・・・・・インナーリード部% 
Bo・・・・・・アウターリード部、t・・・・・・リ
ードフレーム厚寸法、T・・・・・・放熱部属寸法。
FIG. 1 is a plan view of an integrated circuit mounting tape for explaining the first embodiment of the present invention, FIG. 2 is a sectional view taken along the line AA' in FIG. 1, and FIGS. c) is LSI by TAB method
4 is a plan view for explaining the second embodiment of the present invention, and FIG. B-B
6 is a plan view according to the prior art, and FIG. 7 is a sectional view taken along line C-C' in FIG. 6. 1... LSI chip, 2... bump,
3... Lead frame, 4... Heat radiation part, 5... Device hole, 6... Sprocket hole, 7... Polyimide film,
8...Adhesive, 9...Plated wiring, 1
0...Bonding tool, P...Pitch between leads %BI...Inner lead part %
Bo: outer lead part, t: lead frame thickness dimension, T: heat dissipation part dimension.

Claims (1)

【特許請求の範囲】 1、大規模集積回路チップ表面の周縁部に形成された複
数個のバンプに、対応する複数のリードフレームを一括
してボンディング接続して成る集積回路実装用テープに
おいて、前記リードフレームを含む実装用テープが同一
金属材料で形成され、かつ、前記リードフレームが形成
されたデバイスホールの周囲を取り囲むように形成され
た放熱部を有することを特徴とする集積回路実装用テー
プ。 2、前記放熱部がリードフレームの厚さよりも厚く形成
されていることを特徴とする特許請求の範囲第1項記載
の集積回路実装用テープ。 3、前記放熱部が前記デバイスホールを取り囲む数条の
厚膜金属部から形成されていることを特徴とする特許請
求の範囲第1項記載の集積回路実装用テープ。
[Scope of Claims] 1. An integrated circuit mounting tape comprising a plurality of corresponding lead frames collectively bonded to a plurality of bumps formed on the periphery of a surface of a large-scale integrated circuit chip. 1. A tape for mounting an integrated circuit, characterized in that the mounting tape including a lead frame is made of the same metal material and has a heat dissipation part formed to surround a device hole in which the lead frame is formed. 2. The integrated circuit mounting tape according to claim 1, wherein the heat dissipation portion is formed to be thicker than the lead frame. 3. The integrated circuit mounting tape according to claim 1, wherein the heat dissipation section is formed from several thick film metal sections surrounding the device hole.
JP1217928A 1989-08-23 1989-08-23 Tape for mounting integrated circuit Pending JPH0380552A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1217928A JPH0380552A (en) 1989-08-23 1989-08-23 Tape for mounting integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1217928A JPH0380552A (en) 1989-08-23 1989-08-23 Tape for mounting integrated circuit

Publications (1)

Publication Number Publication Date
JPH0380552A true JPH0380552A (en) 1991-04-05

Family

ID=16711920

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1217928A Pending JPH0380552A (en) 1989-08-23 1989-08-23 Tape for mounting integrated circuit

Country Status (1)

Country Link
JP (1) JPH0380552A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS501625A (en) * 1972-11-16 1975-01-09
JPS568863A (en) * 1979-07-02 1981-01-29 Mitsubishi Electric Corp Substrate for semiconductor device
JPH02177342A (en) * 1988-12-27 1990-07-10 Nec Corp Tape for mounting integrated circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS501625A (en) * 1972-11-16 1975-01-09
JPS568863A (en) * 1979-07-02 1981-01-29 Mitsubishi Electric Corp Substrate for semiconductor device
JPH02177342A (en) * 1988-12-27 1990-07-10 Nec Corp Tape for mounting integrated circuit

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