JPH0380698U - - Google Patents
Info
- Publication number
- JPH0380698U JPH0380698U JP14091689U JP14091689U JPH0380698U JP H0380698 U JPH0380698 U JP H0380698U JP 14091689 U JP14091689 U JP 14091689U JP 14091689 U JP14091689 U JP 14091689U JP H0380698 U JPH0380698 U JP H0380698U
- Authority
- JP
- Japan
- Prior art keywords
- step pulse
- signal
- circuit
- switching
- pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Control Of Stepping Motors (AREA)
Description
第１，２図は本考案に係るステツプパルス切換
回路の一実施例を示す図であり、第１図はその回
路構成図、第２図ａ〜ｅは第１図の各部における
信号のタイミングチヤートである。第３図〜第５
図は従来のステツプパルス切換回路を示す図であ
り、第３図はソフトウエア上でパルス幅の切換制
御を行う場合の回路構成図、第４図はハードウエ
ア上でパルス幅の切換制御を行う場合の回路構成
図、第５図ａ〜ｅは第４図の各部における信号の
タイミングチヤートである。
１１…ステツプパルス切換回路、１２…遅延回
路（切換タイミング設定回路）、｛１３…フリツ
プフロツプ回路、１４，１５…アンド回路、１６
…オア回路｝（ステツプパルス変更回路）、ＳＴ
１〜ＳＴｎ…タイミング設定端子。
1 and 2 are diagrams showing an embodiment of the step pulse switching circuit according to the present invention, FIG. 1 is a circuit configuration diagram thereof, and FIGS. 2 a to 2 e are timing charts of signals in each part of FIG. 1. It is. Figures 3 to 5
The figure shows a conventional step pulse switching circuit, Fig. 3 is a circuit configuration diagram when pulse width switching is controlled on software, and Fig. 4 is a circuit configuration diagram when pulse width switching is controlled on hardware. 5A to 5E are timing charts of signals in each part of FIG. 4. 11... Step pulse switching circuit, 12... Delay circuit (switching timing setting circuit), {13... Flip-flop circuit, 14, 15... AND circuit, 16
...OR circuit} (step pulse change circuit), ST
1 ~ STn ...Timing setting terminal.
補正 平２．３．５
図面の簡単な説明を次のように補正する。
明細書第１１頁第５行目から第６行目に「第２
図ａ〜ｅは……である。」とあるのを、「第２図
は第１図のステツプパルス切換回路において入力
されるＳＴＥＰ ＣＨＧ信号と、ＳＴＥＰ１信号
と、ＳＴＥＰ２信号と、遅延回路のＳＴ端子から
出力されるＳＴＥＰ ＫＩＮＤ信号およびオア回
路から出力されるＳＴＥＰ信号の関係を示すタイ
ミングチヤートである。」と補正する。
明細書第１１頁第１１行目から第１３行目に「
第５図ａ〜ｅは……である。」とあるのを、「第
５図は第４図の従来のステツプパルス切換回路に
おいて入力されるＳＴＥＰ ＣＨＧ信号と、ＳＴ
ＥＰ１信号と、ＳＴＥＰ２信号と、フリツプフロ
ツプ回路から出力されるＳＴＥＰ ＫＩＮＤ信号
およびオア回路から出力されるＳＴＥＰ信号の関
係を示すタイミングチヤートである。」と補正す
る。Amendment 2.3.5 The brief description of the drawing is amended as follows. From line 5 to line 6 of page 11 of the specification, it is written as “Second
Figures a to e are... "Figure 2 shows the STEP CHG signal, STEP1 signal, STEP2 signal input to the step pulse switching circuit of Figure 1, the STEP KIND signal output from the ST terminal of the delay circuit, and the OR This is a timing chart showing the relationship between STEP signals output from the circuit.'' From page 11, line 11 to line 13 of the specification, “
Figures a to e are... ”, “Figure 5 shows the STEP CHG signal input in the conventional step pulse switching circuit of Figure 4 and the STEP
This is a timing chart showing the relationship between the EP1 signal, the STEP2 signal, the STEP KIND signal output from the flip-flop circuit, and the STEP signal output from the OR circuit. ” he corrected.
Claims (1)
録動作状態に応じて記録紙の搬送速度を切り換え
るステツピングモータ等の駆動制御に用いられ、
該ステツピングモータを駆動するステツプパルス
信号のパルス幅を切り換えるステツプパルス切換
回路において、前記記録動作状態に基づいて前記
パルス幅を切り換える切換信号を生成するととも
に、前記搬送速度に応じて切換信号を出力する複
数の出力タイミングを設定する切換タイミング設
定回路と、前記ステツプパルス信号を生成すると
ともに、該切換信号が出力されると、該ステツプ
パルス信号のパルス幅を変更するステツプパルス
変更回路と、を設けたことを特徴とするステツプ
パルス切換回路。 It is used for drive control of stepping motors, etc. that change the conveyance speed of recording paper according to the recording operation state when conveying recording paper in printer devices, etc.
A step pulse switching circuit that switches the pulse width of a step pulse signal that drives the stepping motor generates a switching signal that switches the pulse width based on the recording operation state, and outputs a switching signal according to the conveyance speed. and a step pulse changing circuit that generates the step pulse signal and changes the pulse width of the step pulse signal when the switching signal is output. A step pulse switching circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14091689U JPH0380698U (en) | 1989-12-05 | 1989-12-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14091689U JPH0380698U (en) | 1989-12-05 | 1989-12-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0380698U true JPH0380698U (en) | 1991-08-19 |
Family
ID=31687853
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14091689U Pending JPH0380698U (en) | 1989-12-05 | 1989-12-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0380698U (en) |
-
1989
- 1989-12-05 JP JP14091689U patent/JPH0380698U/ja active Pending
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