JPH03808B2 - - Google Patents
Info
- Publication number
- JPH03808B2 JPH03808B2 JP60114689A JP11468985A JPH03808B2 JP H03808 B2 JPH03808 B2 JP H03808B2 JP 60114689 A JP60114689 A JP 60114689A JP 11468985 A JP11468985 A JP 11468985A JP H03808 B2 JPH03808 B2 JP H03808B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- collector
- input
- whose
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
- H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は論理回路、特にECL型Ｒ−Ｓフリツ
プフロツプ回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to logic circuits, particularly to ECL type R-S flip-flop circuits.
従来、この種のＲ−Ｓフリツプフロツプ回路は
第２図に示すように、２入力NORゲート１，２
を２個用いそれぞれの出力を他方のNORゲート
の入力の一つに接続し、残りの入力の一方をＲ入
力すなわちリセツト入力、他方をＳ入力すなわち
セツト入力とした構成となつていた。
Conventionally, this type of R-S flip-flop circuit has two input NOR gates 1 and 2, as shown in FIG.
The configuration was such that the output of each was connected to one of the inputs of the other NOR gate, and one of the remaining inputs was used as the R input, that is, the reset input, and the other as the S input, that is, the set input.
このＲ，Ｓ入力端子を共に禁止状態の高レベル
電圧（以下“１”と略記）から維持状態の低レベ
ル電圧（以下“０”と略記）に信号を加えた時
Ｑ，出力端子の出力が“０”から“１”に変化
して、NORゲートの各入力に入り、その結果Ｑ，
Ｑ出力端子の出力は再度“０”になり、この
“０”，“１”がくり返すという発振が起こる。 When a signal is applied to both the R and S input terminals from a high level voltage (hereinafter abbreviated as "1") in the inhibited state to a low level voltage (hereinafter abbreviated as "0") in the maintained state, the output of the Q output terminal changes. changes from “0” to “1” and enters each input of the NOR gate, resulting in Q,
The output of the Q output terminal becomes "0" again, and oscillation occurs in which "0" and "1" are repeated.
第３図は第２図に示したＲ−Ｓフリツプフロツ
プ回路のより詳細なECL型フリツプフロツプの
回路図を示すNORゲート１はトランジスタQ4，
Q5，Q6，Q8等から構成され、NORゲート２はト
ランジスタQ1，Q2，Q3，Q7等から構成されてい
る。 FIG. 3 shows a more detailed ECL type flip-flop circuit diagram of the R-S flip-flop circuit shown in FIG. 2. NOR gate 1 is a transistor Q 4 ,
The NOR gate 2 is composed of transistors Q 1 , Q 2 , Q 3 , Q 7 and the like.
上述した従来のＲ−Ｓフリツプフロツプ回路は
Ｒ，Ｓ入力を“１”に設定し、両入力を同時に
“０”に変化させた時、発振が起こるという欠点
がある。
The conventional R-S flip-flop circuit described above has a drawback that oscillation occurs when the R and S inputs are set to "1" and both inputs are changed to "0" at the same time.
本発明の目的はこの発振を防いだフリツプフロ
ツプ回路を提供することにある。 An object of the present invention is to provide a flip-flop circuit that prevents this oscillation.
本発明のＲ−Ｓフリツプフロツプ回路は、Ｒ及
びＳ入力を“１”に設定した時、Ｒ入力（もしく
はＳ入力）を優先させ肯定出力を“０”（もしく
は否定出力“０”）に定める為に、ベースがセツ
ト入力端子に、コレクタが第１の抵抗を介して電
源端子に接続されている第１のトランジスタと、
ベースが第１の基準電源に接続され、コレクタが
第２の抵抗を介して電源端子へ接続されている第
２のトランジスタと、ベースが肯定出力端子に、
コレクタが前記第１のトランジスタのコレクタ
に、エミツタは前記第１及び第２のトランジスタ
のエミツタと共通接続されている第３のトランジ
スタと、ベースが第２の基準電源に、コレクタが
前記第１、第２、第３のトランジスタりエミツタ
に接続されている第４のトランジスタと、ベース
がリセツト端子にコレクタが前記第２のトランジ
スタのコレクタに、エミツタが前記第４のトラン
ジスタと共に第１の定電流源へ接続されている第
５のトランジスタと、ベースが前記第２のトラン
ジスタのコレクタに、コレクタが電源端子に、エ
ミツタが前記肯定出力端子並びに第２の定電流源
へ接続されている第６のトランジスタと、ベース
が前記第１のトランジスタのコレクタに、コレク
タが電源端子にエミツタが第３の定電流源並びに
否定出力端子に接続された第７のトランジスタと
を有している。
The R-S flip-flop circuit of the present invention gives priority to the R input (or S input) and sets the positive output to "0" (or negative output "0") when the R and S inputs are set to "1". a first transistor having a base connected to a set input terminal and a collector connected to a power supply terminal via a first resistor;
a second transistor having a base connected to the first reference power supply, a collector connected to the power supply terminal via a second resistor, and a base connected to the positive output terminal;
a third transistor whose collector is connected to the collector of the first transistor, whose emitter is commonly connected to the emitters of the first and second transistors; whose base is connected to the second reference power source; and whose collector is connected to the first transistor; A fourth transistor is connected to the emitters of the second and third transistors, has a base connected to a reset terminal, a collector connected to the collector of the second transistor, and an emitter connected to the fourth transistor and a first constant current source. a fifth transistor whose base is connected to the collector of the second transistor, whose collector is connected to the power supply terminal, and whose emitter is connected to the positive output terminal and the second constant current source. and a seventh transistor whose base is connected to the collector of the first transistor, whose collector is connected to the power supply terminal, and whose emitter is connected to the third constant current source and the negative output terminal.
次に、本発明について図面を参照して説明す
る。
Next, the present invention will be explained with reference to the drawings.
第１図はECL回路構成のＳ入力優先回路を備
えたＲ−Ｓフリツプフロツプ回路である。今Ｓ入
力端子に“１”、Ｒ入力端子に“０”の信号を加
えると、トランジスタQ9，Q11，Q12が導通状態
（以下“ON”と略記）となり、トランジスタ
Q10，Q13は遮断状態（以下“OFF”と略記）と
なる為、出力端子Ｑには“１”、出力端子には
“０”が出力される。この状態より、Ｓ入力端子
の信号を“１”から“０”へ変化させた時、トラ
ンジスタQ9は“OFF”するが、トランジスタQ11
はベースが出力端子Ｑの“１”へ接続されている
為にONを維持する。その為に、出力端子Ｑ，
は“１”，“０”のままでありＳ入力が“１”、Ｒ
入力が“０”の状態を維持する。 FIG. 1 shows an R-S flip-flop circuit equipped with an S input priority circuit having an ECL circuit configuration. Now, if a signal of "1" is applied to the S input terminal and "0" to the R input terminal, transistors Q 9 , Q 11 , and Q 12 become conductive (hereinafter abbreviated as "ON"), and the transistors
Since Q 10 and Q 13 are in a cutoff state (hereinafter abbreviated as "OFF"), "1" is output to the output terminal Q and "0" is output to the output terminal. In this state, when the signal at the S input terminal changes from "1" to "0", transistor Q 9 turns "OFF", but transistor Q 11
remains ON because the base is connected to output terminal Q “1”. Therefore, the output terminal Q,
remain “1” and “0”, and S input is “1” and R
The input remains at “0”.
又、Ｒ入力端子に“１”、Ｓ入力端子に“０”
の信号を加えるとトランジスタQ13がONし、ト
ランジスタQ9，Q10，Q11及びQ12はOFFとなり、
出力端子Ｑには“０”、出力端子には“１”が
出力される。この状態よりＲ入力端子の信号を
“１”から“０”へ変化させた時、トランジスタ
Q13が“OFF”し、トランジスタQ12が“ON”す
るが、トランジスタQ9及びQ11も“OFF”してい
るので、トランジスタQ10がONする。その為に、
出力Ｑ，はＳ入力が“０”、Ｒ入力が“１”の
状態を維持する。 Also, “1” is input to the R input terminal and “0” is input to the S input terminal.
When the signal is applied, transistor Q13 turns on, transistors Q9 , Q10 , Q11 and Q12 turn off,
“0” is output to the output terminal Q, and “1” is output to the output terminal. In this state, when the signal at the R input terminal changes from "1" to "0", the transistor
Q 13 is turned “OFF” and transistor Q 12 is turned “ON”, but since transistors Q 9 and Q 11 are also “OFF”, transistor Q 10 is turned ON. For that reason,
The output Q maintains the state that the S input is "0" and the R input is "1".
したがつてこの回路は通常のＲ−Ｓフリツプフ
ロツプの動作を行う。 This circuit thus performs the operation of a conventional R-S flip-flop.
次にＲ，Ｓ両入力端子に入力禁止信号の“１”
を入れた場合、トランジスタQ13がONし、トラ
ンジスタQ9，Q10，Q11，E12がOFFするので、出
力端子Ｑ，はそれぞれ“０”，“１”となり、リ
セツト状態、すなわちＲ入力に“１”Ｓ入力に
“０”の信号を加えた時と同じになる。この状態
より、Ｒ，Ｓ両入力端子を同時に“０”にする
と、トランジスタQ9，Q11，Q13がOFFし、トラ
ンジスタQ10，Q12が“ON”するために、出力端
子Ｑは“０”、出力端子は“１”となる。 Next, input prohibition signal “1” is applied to both R and S input terminals.
When the transistor Q13 is turned on and the transistors Q9 , Q10 , Q11 , and E12 are turned off, the output terminals Q become "0" and "1", respectively, and are in the reset state, that is, the R input This is the same as adding a "0" signal to the "1" S input. In this state, when both the R and S input terminals are set to "0" at the same time, the transistors Q 9 , Q 11 , and Q 13 are turned OFF, and the transistors Q 10 and Q 12 are turned "ON", so that the output terminal Q is set to "0". 0”, and the output terminal becomes “1”.
したがつて、従来のＲ−Ｓフリツプフロツプ回
路で問題となつていれＲ，Ｓ入力を同時に“１”
から“０”に変化させた時の発振という現象は、
起らなくなる。又Ｒ入力をＳ入力に、Ｓ入力をＲ
入力に、出力端子Ｑ，の各出力も同様に入れ替
えて、Ｒ，Ｓ両入力端子に入力禁止の“１”の信
号を加えた時、出力がセツト状態、すなわちＳ入
力に“１”、Ｒ入力に“０”の信号を加えた時と
同じ状態にしても、同じ機能が得られることは言
うまでもない。 Therefore, a problem with conventional R-S flip-flop circuits is that the R and S inputs must be set to "1" at the same time.
The phenomenon of oscillation when changing from to “0” is
It won't happen. Also, the R input becomes the S input, and the S input becomes the R input.
When the inputs and the outputs of the output terminals Q and Q are interchanged in the same way, and a signal of "1" that prohibits input is applied to both the R and S input terminals, the output is in the set state, that is, the S input is "1" and the R input terminal is "1". It goes without saying that the same function can be obtained even if the state is the same as when a "0" signal is applied to the input.
以上説明したように本発明の回路によれば、
Ｒ，Ｓ入力端子が共に“１”から“０”に変化し
ても発振がなく、従来回路より素子数を少なくし
たところのフリツプフロツプが得られる。
As explained above, according to the circuit of the present invention,
Even if both the R and S input terminals change from "1" to "0", there is no oscillation, and a flip-flop with fewer elements than the conventional circuit can be obtained.
第１図は本発明の一実施例を示す回路図、第２
図は従来のＲ−Ｓフリツプフロツプ回路のブロツ
ク図、第３図はその回路図である。
R1，R2……抵抗、Q1〜Q15……トランジスタ、
I1〜I4……定電流源、VRF1，VRF2……定電圧源、
Ｒ……リセツト入力端子、Ｓ……セツト入力端
子、Ｑ……肯定出力端子、……否定出力端子、
VCC……電源端子、GND……接地端子。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a block diagram of a conventional R-S flip-flop circuit, and FIG. 3 is its circuit diagram. R 1 , R 2 ... Resistor, Q 1 to Q 15 ... Transistor,
I 1 to I 4 ... constant current source, V RF1 , V RF2 ... constant voltage source,
R...Reset input terminal, S...Set input terminal, Q...Positive output terminal,...Negative output terminal,
V CC ...Power supply terminal, GND...Grounding terminal.
Claims (1)
の抵抗を介して電源端子に接続されている第１の
トランジスタと、ベースが第１の基準電源に接続
され、コレクタが第２の抵抗を介して電源端子へ
接続されている第２のトランジスタと、ベースが
肯定出力端子に、コレクタが前記第１のトランジ
スタのコレクタに、エミツタは前記第１及び第２
のトランジスタのエミツタと共通接続している第
３のトランジスタと、ベースが第２の基準電源
に、コレクタが前記第１、第２及び第３のトラン
ジスタのエミツタに接続されている第４のトラン
ジスタと、ベースがリセツト端子に、コレクタが
前記第２のトランジスタのコレクタにエミツタが
前記第４のトランジスタのエミツタと共に第１の
定電流源へ接続されている第５のトランジスタ
と、ベースが前記第２のトランジスタのコレクタ
に、コレクタが電源端子に、エミツタが前記肯定
出力端子並びに第２の定電流源へ接続されている
第６のトランジスタと、ベースが前記第１のトラ
ンジスタのコレクタに、コレクタが電源端子に、
エミツタが第３の定電流源並びに否定出力端子に
接続された第７のトランジスタを有することを特
徴とするフリツプフロツプ回路。1 The base is the set input terminal, the collector is the first
a first transistor connected to the power supply terminal through a resistor; and a second transistor whose base is connected to the first reference power supply and whose collector is connected to the power supply terminal through a second resistor. , whose base is connected to the positive output terminal, whose collector is connected to the collector of the first transistor, and whose emitter is connected to the first and second transistors.
a third transistor commonly connected to the emitters of the transistors; and a fourth transistor whose base is connected to the second reference power supply and whose collector is connected to the emitters of the first, second, and third transistors. , a fifth transistor whose base is connected to the reset terminal, whose collector is connected to the collector of the second transistor, and whose emitter is connected to the first constant current source together with the emitter of the fourth transistor; a sixth transistor, the collector of which is connected to the power supply terminal, the emitter of which is connected to the positive output terminal and the second constant current source; the base of which is connected to the collector of the first transistor, and whose collector is connected to the power supply terminal; To,
A flip-flop circuit comprising a seventh transistor whose emitter is connected to a third constant current source and a negative output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60114689A JPS61273012A (en) | 1985-05-28 | 1985-05-28 | Flip-flop circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60114689A JPS61273012A (en) | 1985-05-28 | 1985-05-28 | Flip-flop circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61273012A JPS61273012A (en) | 1986-12-03 |
| JPH03808B2 true JPH03808B2 (en) | 1991-01-09 |
Family
ID=14644171
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60114689A Granted JPS61273012A (en) | 1985-05-28 | 1985-05-28 | Flip-flop circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61273012A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09153593A (en) * | 1995-11-30 | 1997-06-10 | Nec Corp | Bimos logic circuit |
-
1985
- 1985-05-28 JP JP60114689A patent/JPS61273012A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61273012A (en) | 1986-12-03 |
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