JPH0381240B2 - - Google Patents

Info

Publication number
JPH0381240B2
JPH0381240B2 JP58015660A JP1566083A JPH0381240B2 JP H0381240 B2 JPH0381240 B2 JP H0381240B2 JP 58015660 A JP58015660 A JP 58015660A JP 1566083 A JP1566083 A JP 1566083A JP H0381240 B2 JPH0381240 B2 JP H0381240B2
Authority
JP
Japan
Prior art keywords
cell
current
switch element
branch
flowing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58015660A
Other languages
Japanese (ja)
Other versions
JPS59142796A (en
Inventor
Ichiro Ishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP58015660A priority Critical patent/JPS59142796A/en
Publication of JPS59142796A publication Critical patent/JPS59142796A/en
Publication of JPH0381240B2 publication Critical patent/JPH0381240B2/ja
Granted legal-status Critical Current

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Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Description

【発明の詳細な説明】 本発明は一般的には少なくとも一つの情報を循
環電流の形で記憶するジヨセフソン記憶回路の駆
動方法に関する。より具体的には記憶された2進
情報を非破壊的に読み出すこと(以下NDROと
言う)が可能なジヨセフン記憶回路に関する。更
に特定すれば、本発明は上記記憶回路において超
伝導閉ループを形成している分枝の対の1つに1
つの書き込みゲートを有するジヨセフソン
NDRO記憶回路に関するものである。更に特定
すれば本発明は上記記憶回路において、第1のゲ
ートの制御線に連結して第2のゲートを配置した
ジヨセフソンNDRO記憶回路の駆動方法に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention generally relates to a method of driving a Josephson storage circuit that stores at least one piece of information in the form of a circulating current. More specifically, the present invention relates to a storage circuit capable of non-destructively reading out stored binary information (hereinafter referred to as NDRO). More specifically, the present invention provides a superconducting closed loop in one of the pairs of branches forming a superconducting closed loop in the storage circuit.
Josefson with two write gates
This relates to the NDRO storage circuit. More specifically, the present invention relates to a method for driving a Josephson NDRO memory circuit in which a second gate is connected to the control line of the first gate in the memory circuit.

ジヨセフソンNDRO記憶回路は例えば文献ジ
ヤーナル オブ アブライド フイジツクス誌
(Journal of Applied Physics)Vol,50No.
12December1979PP、8143〜8169を参照すればわ
かるように、当業者には広く知られている。
The Josephson NDRO memory circuit is described in, for example, the literature Journal of Applied Physics Vol. 50 No.
12 December 1979 PP, 8143-8169, are well known to those skilled in the art.

第1図はジヨセフソンNDRO記憶回路の従来
例の一つを説明するための図である。この例では
超伝導ループ2に循環電流Icircが保持されてい
るか否かで2進情報を記憶させるジヨセフソン
NDRO記憶回路の2×2アレイを示す。
FIG. 1 is a diagram for explaining one of the conventional examples of Josephson NDRO storage circuit. In this example, Josephson stores binary information depending on whether or not the circulating current Icirc is held in superconducting loop 2.
A 2x2 array of NDRO storage circuits is shown.

循環電流IcircをAの超伝導ループ2に保持さ
せるためには、Aに関係する列ライン5にバイア
ス電流IyとAに関係する制御線6と7にそれぞれ
制御電流Iy′とIyとをそれぞれAに関係する電源
10,11,12から同時に流す。この事により
Aの記憶セル1が指定され、且つ上記制御線6と
7をそれぞれ流れる制御電流IyとIxはともにAの
スイツチ素子8に制御磁界を与えるように構成さ
れているため、制御電流Iy′とIxを同時に流す事
によりAの記憶セル1に含まれるスイツチ素子8
は一時電圧状態になる。その結果Aの超伝導閉ル
ープ2に注入された電流Iyの内Aスイツチ素子8
を含む分枝3に流れる最低駆動電流Iminを差し
引いた残りはAのスイツチ素子8を含まない分枝
4に流れしかる後にIy,Iy′とIxを0にすればA
の超伝導閉ループ2内に時計回りの循環電流
Icircを保持する。
In order to maintain the circulating current Icirc in the superconducting loop 2 of A, a bias current Iy is applied to the column line 5 related to A, and control currents Iy' and Iy are applied to the control lines 6 and 7 related to A, respectively. simultaneously from the power supplies 10, 11, and 12 related to the. As a result, the memory cell 1 of A is designated, and since the control currents Iy and Ix flowing through the control lines 6 and 7, respectively, are configured to apply a control magnetic field to the switch element 8 of A, the control current Iy ' and Ix at the same time, the switch element 8 included in the memory cell 1 of A
becomes a temporary voltage state. As a result, of the current Iy injected into the superconducting closed loop 2 of A, the A switch element 8
After subtracting the lowest drive current Imin flowing through branch 3 that includes switch element 8, the remainder flows to branch 4 that does not include switch element 8 of A. After that, if Iy, Iy' and Ix are set to 0, then A
A clockwise circulating current in the superconducting closed loop 2 of
Hold Icirc.

循環電流IcircをAの超伝導ループ2に保持し
ない状態を実現するためには、Aに関係する列ラ
イン5にバイアス電流Iyを流す事なくAに関係す
る制御線6と7にそれぞれ制御電流Iy′とIyとを
それぞれAに関係する電源11、12から同時に
流した後、制御電流Iy′とIxを0にする。その結
果Aの超伝導閉ループ2に循環電流Icircは残ら
ない。
In order to realize a state in which the circulating current Icirc is not held in the superconducting loop 2 of A, the control current Iy is applied to the control lines 6 and 7 related to A without flowing the bias current Iy to the column line 5 related to A. ' and Iy are made to flow simultaneously from the power supplies 11 and 12 related to A, respectively, and then the control currents Iy' and Ix are set to zero. As a result, no circulating current Icirc remains in the superconducting closed loop 2 of A.

Aの超伝導閉ループ2に循環電流Icircが保持
されている状態はAに関係する列ライン5に電流
IyをAに関係する読み出し線15に、電流Isをそ
れぞれ同時に流し、Aの記憶セル1を指定すれば
Aの分枝4を流れる電流(1−K)Iyと上記循環
電流Icircとの和電流(1−K)Iy+Icircの作る
磁界により、Aの分枝4と電磁的に結合している
Aのスイツチ素子9を電圧状態とし、この状態が
Aに関係する検出器14により検出されて読み取
られる。但しK≡(分枝4の自己インダクタン
ス)/(分枝3と分枝4の自己インダクタンスの
和)である。
The state in which the circulating current Icirc is maintained in the superconducting closed loop 2 of A is the current in the column line 5 related to A.
If current Is is simultaneously applied to the readout line 15 related to A, and memory cell 1 of A is designated, the current (1-K) flowing through branch 4 of A is the sum of Iy and the above circulating current Icirc. (1-K) The magnetic field created by Iy + Icirc sets the switch element 9 of A, which is electromagnetically coupled to the branch 4 of A, into a voltage state, and this state is detected and read by the detector 14 related to A. . However, K≡(self-inductance of branch 4)/(sum of self-inductance of branch 3 and branch 4).

循環電流Icircが保持されていない状態はAに
関係する列ライン5に電流Iy、Aに関係する読み
出し線15に電流Isをそれぞれ同時に流しAの記
憶セル7を指定すれば、Aの分枝4を流れる電流
(1−K)Iyのみの作る磁界によりAの分枝4と
電磁的に結合しているAのスイツチ素子9は零電
圧状態を維持し、この状態がAに関係する検出器
14により検出されて読み取られる。
In a state where the circulating current Icirc is not held, if the current Iy is applied to the column line 5 related to A, and the current Is is applied to the readout line 15 related to A at the same time, and the memory cell 7 of A is specified, the branch 4 of A is The switch element 9 of A, which is electromagnetically coupled to the branch 4 of A, maintains a zero voltage state due to the magnetic field created only by the current (1-K) Iy flowing through it, and this state causes the detector 14 related to A to maintain a zero voltage state. detected and read by

上記のメモリ回路構成では各セルについて行ラ
インとして制御電流Ixを流す為の制御線7と、読
み出し電流Isを流すための読み出し線15の2本
のラインが必要で、且つそれぞれのラインに電源
を必要とし、複雑な回路構成であるので第2図に
示すような簡素化されたジヨセフソンNDRO記
憶回路が考えられる。
In the above memory circuit configuration, two lines are required for each cell: a control line 7 for flowing a control current Ix as a row line, and a read line 15 for flowing a read current Is, and each line is connected to a power source. Since this requires a complicated circuit configuration, a simplified Josephson NDRO memory circuit as shown in FIG. 2 can be considered.

すなわち第1の分枝3と第2の分枝4から成る
超伝導閉ループと該第1の分枝3中に配置された
ジヨセフソン電流を流しうる第1のスイツチ素子
8と、該第1のスイツチ素子8と電磁的に結合す
るように配置された制御線7と、該第2の分枝4
と電磁的に結合するように配置されたジヨセフソ
ン電流を流しうる第2のスイツチ素子9とから成
り該第1のスイツチ素子8を書き込みゲートとし
て用いて、情報を該超伝導閉ループ2に貯え該第
2のスイツチ素子9を読み出しゲートとして用い
るジヨセフソン記憶装置において、該第1のスイ
ツチ素子8の制御線に連結して該第2のスイツチ
素子9を配置した簡素化されたジヨセフソン
NDRO記憶回路が考えられる。
That is, a superconducting closed loop consisting of a first branch 3 and a second branch 4, a first switch element 8 arranged in the first branch 3 and capable of passing Josephson current, and the first switch a control line 7 arranged to be electromagnetically coupled to the element 8; and the second branch 4.
and a second switch element 9 through which Josephson current can flow, which is arranged so as to be electromagnetically coupled to the superconducting closed loop 2. The first switch element 8 is used as a write gate to store information in the superconducting closed loop 2. In a Josephson memory device using a second switch element 9 as a read gate, a simplified Josephson memory device in which the second switch element 9 is connected to the control line of the first switch element 8 is arranged.
An NDRO storage circuit is considered.

本発明の目的は該簡素化されたジヨセフソン
NDRO記憶回路の知られていない駆動方法を堤
供する事にある。
The object of the present invention is to simplify the
The purpose is to provide an unknown driving method for the NDRO memory circuit.

本発明によれば第1の分枝と第2の分枝から成
る超伝導閉ループと上記第1の分枝中に配置され
たジヨセフソン電流を流しうる第1のスイツチ素
子と、上記第1のスイツチ素子と電磁的に結合す
るように配置された複数の制御線と該制御線の内
の少なくとも一本の制御線と連結し、上記第2の
分枝と電磁的に結合するように配置されたジヨセ
フソン電流を流しうる第2のスイツチ素子とから
成り、上記第1のスイツチ素子を書き込みゲート
として用いて流れる向きの異なる循環電流として
か、あるいは循環電流の有無として2進情報を上
記超伝導閉ループに貯え、上記第2のスイツチ素
子を読み出しゲートとして用いるジヨセフソン記
憶回路の駆動に於いて、上記第2のスイツチ素子
が連結した上記第1のスイツチ素子の制御線に流
れる電流が書き込み時と読み出し時とで同じ事を
特徴とするジヨセフソン記憶回路の駆動法が得ら
れる。
According to the present invention, a superconducting closed loop consisting of a first branch and a second branch, a first switch element arranged in the first branch and capable of flowing Josephson current, and a superconducting closed loop comprising a first branch and a second branch; A plurality of control lines arranged to be electromagnetically coupled to the element, coupled to at least one control line among the control lines, and arranged so as to be electromagnetically coupled to the second branch. and a second switch element through which Josephson current can flow, and the first switch element is used as a write gate to transfer binary information into the superconducting closed loop as circulating currents flowing in different directions or as circulating currents. In driving a Josephson memory circuit that uses the second switch element as a read gate, the current flowing through the control line of the first switch element connected to the second switch element is different during writing and reading. A method for driving a Josephson memory circuit featuring the same characteristics is obtained.

以下図面を参照して本発明を詳細に説明する。
本発明の原理は、それぞれ第3図a,bに示す制
御特性すなわち、 イ (1−K)Iyの大きさの制御電流に対して零
電圧状態にあり、(1−K)Iy+Icircの制御電
流に対して電圧状態にあるゲート電流Ixが存在
する特性(第3図b) ロ 上記Ixを第1の制御電流とし、該制御電流に
対してはゲート電流がKIyの場合とKIy+Icirc
の場合に零電圧状態にあり、Iy′を第2の制御
電流とし、該制御電流に対しては、ゲート電流
がKIyの場合にもKIy+Icircの場合にも零電圧
状態にあり、第1の制御電流と第2の制御電流
が同時に流れた場合の制御電流Ix+Iy′に対し
ては、ゲート電流がKIyの場合にもKIy+Icirc
の場合にも電圧状態にある特性(第3図a図に
はIxとIy′が同じ大きさとして示されているが
これは必要な条件ではない) を有する2つのスイツチ素子をそれぞれ第2図に
示す如くイの特性を有するスイツチ素子を読み出
しゲートとして超伝導ループ2内の第2の分枝4
と電磁的に結合したスイツチ素子9に用い、ロの
特性を有するスイツチ素子を書き込みゲートとし
て超伝導閉ループ2内の第1の分枝3内に制御線
6,7と電磁的に結合したスイツチ素子8に用い
る事にある。但しIyは列ライン5を流れ超伝導閉
ループ2に流入するセル電流であり、Kは(分枝
4の自己インダクタンス)/(分枝3と分枝4の
自己インダクタンスの和)より求まる回路定数で
ある。Icircは超伝導閉ループ2に保持される右
回りの循環電流であり、スイツチ素子8の最低駆
動電流をIminとすればその大きさは|KIy−
Imin|に等しい。Ixは行ライン7を流れる電流
であり、Iy′は列ライン6を流れる制御電流であ
る。
The present invention will be described in detail below with reference to the drawings.
The principle of the present invention is based on the control characteristics shown in Figure 3a and b, respectively. Characteristics in which there is a gate current Ix in a voltage state for
It is in a zero voltage state when , and Iy' is the second control current, and for this control current, it is in a zero voltage state both when the gate current is KIy and when KIy + Icirc, and the first control For the control current Ix + Iy' when the current and the second control current flow simultaneously, even when the gate current is KIy, KIy + Icirc
(Although Ix and Iy' are shown as having the same magnitude in Figure 3a, this is not a necessary condition), two switch elements with the characteristic of being in a voltage state also in the case of (Figure 3a) are shown in Figure 2. As shown in FIG.
A switch element 9 is used as a switch element 9 which is electromagnetically coupled to the control lines 6 and 7 in the first branch 3 in the superconducting closed loop 2 using the switch element having the characteristic (b) as a write gate. It is used for 8. However, Iy is the cell current flowing through the column line 5 and flowing into the superconducting closed loop 2, and K is the circuit constant determined from (self-inductance of branch 4)/(sum of self-inductance of branches 3 and 4). be. Icirc is a clockwise circulating current maintained in the superconducting closed loop 2, and if the lowest drive current of the switch element 8 is Imin, its magnitude is |KIy−
Equal to Imin|. Ix is the current flowing through row line 7 and Iy' is the control current flowing through column line 6.

次に実例をあげて説明する。第4図は本発明を
説明するための図でジヨセフソンNDRO記憶回
路の2×2アレイを示す。
Next, an example will be given and explained. FIG. 4 is a diagram for explaining the present invention and shows a 2×2 array of Josephson NDRO storage circuits.

スイツチ素子8及び9はそれぞれ第3図a,b
の制御特性を持つように設計される。
Switch elements 8 and 9 are shown in FIG. 3a and b, respectively.
It is designed to have the control characteristics of

セルAに循環電流Icircを書き込む方法を示す。
まず書き込み前のセルAに循環電流が流れていな
い場合(Icirc=0)について述べる。セルAに
関係した列ライン5,6及び行ライン7にそれぞ
れセル電流Iy、制御電流Iy′,Ixをそれぞれ電源
10,11,12から流す。ここで該Iyが該Iy′,
Ixよりも早くセルAの超伝導ループ2に注入され
ると、一時セルAの分枝3,4にはそれぞれ電流
KIy,(1−K)Iyが流れ、その後該Iy′,Iyが流
れるとセルAのスイツチ素子8はその制御特性に
より電圧状態にスイツチし、その結果セルAの分
枝3,4にはそれぞれ電流Imin,Iy−Iminが流
れる。逆に該Iy′,Ixが該Iyより早くセルAに作
用した場合も、セルAのスイツチ素子8は電圧状
態で動作し、その結果セルAの分枝3,4にはそ
れぞれ電流Imin,Iy−Iminが流れる。いずれの
場合もセルAのスイツチ素子9は分枝4に流れる
電流がある値(第3図b,P点)を超えると電圧
状態になりセルAに関係したIxは遮断されるが、
既にセルAのスイツチ素子8は電圧状態にあるの
で、最終的にセルAの分枝3,4にはそれぞれ上
記の電流が流れる。その後どちらの場合も該Iy′,
Ixを0にし更に該Iyを0にすればセルAの超伝導
ループ2には右まわりの循環電流KIy−Iminが流
れる。
A method of writing circulating current Icirc into cell A is shown.
First, the case where no circulating current flows through cell A before writing (Icirc=0) will be described. A cell current Iy and control currents Iy' and Ix are applied to column lines 5 and 6 and row line 7 related to cell A, respectively, from power supplies 10, 11 and 12, respectively. Here, the Iy is the Iy′,
When injected into superconducting loop 2 of cell A earlier than Ix, currents temporarily flow into branches 3 and 4 of cell A, respectively.
When KIy, (1-K)Iy flows, and then Iy', Iy flows, the switch element 8 of cell A switches to the voltage state due to its control characteristics, so that branches 3 and 4 of cell A are supplied with respective voltages. Currents Imin and Iy−Imin flow. Conversely, if Iy' and Ix act on cell A earlier than Iy, the switch element 8 of cell A operates in a voltage state, and as a result, branches 3 and 4 of cell A receive currents Imin and Iy, respectively. -Imin flows. In either case, when the current flowing through the branch 4 exceeds a certain value (Fig. 3b, point P), the switch element 9 of cell A enters a voltage state, and Ix related to cell A is cut off.
Since the switch element 8 of cell A is already in a voltage state, the above-mentioned currents will eventually flow in the branches 3 and 4 of cell A, respectively. Then in both cases, Iy′,
When Ix is set to 0 and Iy is set to 0, a clockwise circulating current KIy-Imin flows through the superconducting loop 2 of cell A.

次に書き込み前のセルAに既にIcirc=KIy−
Iminが流れている場合について述べる。セルA
に関係した列ライン5,6及び行ライン7にそれ
ぞれセル電流Iy、制御電流Iy′,Ixをそれぞれ電
源10,11,12から流す。ここで該Iyが該
Iy′,Ixよりも早くセルAの超伝導ループ2に注
入されると、セルAの分枝3,4にはそれぞれ電
流Imin,Iy−Iminが流れ、その後該Iy′,Ixを流
してもセルAの分枝3,4に流れる電流はそれぞ
れImin,Iy−Iminを維持したままである。一方
該Iyより該Iy′,Ixを先にセルAに作用させると、
セルAのスイツチ素子8はその制御特性により電
圧状態にスイツチし、セルAのIcircは0となり、
その後該Iyを注入すると、セルAの分枝3,4に
流れる電流はそれぞれImin,Iy−Iminとなる。
これ等の場合も、セルAのスイツチ素子9は分枝
4に流れる電流がある値(第3図b,P点)を超
えると電圧状態になり、セルAに関係したIxは遮
断されるが既にセルAのスイツチ素子8は電圧状
態にあるので、最終的にセルAの分枝3,4には
それぞれ上記の電流が流れる。どちらの場合もこ
の後該Iy′,Ixを0にし更に該Iyを0にすればセ
ルAの超伝導ループ2には右まわりの循環電流
KIy−Iminが残る。
Next, Icirc=KIy− is already in cell A before writing.
Let's talk about the case where Imin is flowing. Cell A
A cell current Iy and a control current Iy', Ix are applied to column lines 5, 6 and row line 7, respectively, from power supplies 10, 11, 12, respectively. Here, the Iy is
When injected into the superconducting loop 2 of cell A earlier than Iy′, Ix, currents Imin and Iy−Imin flow in branches 3 and 4 of cell A, respectively, and even if Iy′ and Ix are subsequently applied, The currents flowing in branches 3 and 4 of cell A remain at Imin and Iy-Imin, respectively. On the other hand, if Iy' and Ix are applied to cell A before Iy,
The switch element 8 of cell A switches to a voltage state due to its control characteristics, and Icirc of cell A becomes 0,
When Iy is then injected, the currents flowing through branches 3 and 4 of cell A become Imin and Iy-Imin, respectively.
In these cases, the switch element 9 of cell A becomes a voltage state when the current flowing through branch 4 exceeds a certain value (point P in Figure 3b), and Ix related to cell A is cut off. Since the switch element 8 of cell A is already in a voltage state, the above-mentioned currents will eventually flow in the branches 3 and 4 of cell A, respectively. In either case, if Iy' and Ix are then set to 0 and Iy is set to 0, a clockwise circulating current will be created in superconducting loop 2 of cell A.
KIy−Imin remains.

このようにセルAに循環電流Icircを書き込む
には、書き込み前のセルAの状態によらずセルA
に作用するセル電流Iy、同制御電流Iy′,Ixを任
意の順序で流した後Iy′,Ixを0とし更にIyを0
にする。
In this way, to write the circulating current Icirc to cell A, the cell A
After flowing the cell current Iy acting on the cell current Iy and the control currents Iy′ and Ix in any order, Iy′ and Ix are set to 0, and then Iy is set to 0.
Make it.

この時非選択のセルCにはIyとIy′が作用する
がセルCのスイツチ素子8はその制御特性により
零電圧状態を維持し、IyがセルCに注入されても
Iy=Iy′=0にした後は初期の状態を維持する。
同様に非選択のセルBにはIxが作用するが、セル
Bのスイツチ素子8はその制御特性により零電圧
状態を維持し、セルBの状態には変化がない。
At this time, Iy and Iy' act on unselected cells C, but the switch element 8 of cell C maintains a zero voltage state due to its control characteristics, and even if Iy is injected into cell C,
After setting Iy=Iy′=0, the initial state is maintained.
Similarly, Ix acts on unselected cell B, but the switch element 8 of cell B maintains a zero voltage state due to its control characteristics, and the state of cell B remains unchanged.

セルAに循環電流Icirc=0を書き込む方法を
示す。
A method of writing circulating current Icirc=0 to cell A will be shown.

セルAに関係した列ライン6及び行ライン7に
それぞれ制御電流Iy′,Ixをそれぞれ電源11,
12から流す。その結果セルAのスイツチ素子8
はその制御特性により電圧状態となり、書き込み
前のセルAに循環電流が流れていた場合も、流れ
ていなかつた場合も循環電流Icircは0となる。
その後該Iy′,Ixを0とすればセルAに循環電流
Icirc=0が書き込まれる。
Control currents Iy' and Ix are supplied to the column line 6 and row line 7 related to cell A by power supplies 11 and 11, respectively.
It starts from 12. As a result, switch element 8 of cell A
is in a voltage state due to its control characteristics, and the circulating current Icirc is 0 whether or not a circulating current is flowing through the cell A before writing.
After that, if Iy' and Ix are set to 0, a circulating current flows through cell A.
Icirc=0 is written.

この時非選択のセルB、及びセルCはそれぞれ
Ix又はIy′のみが作用し、それぞれのセルのスイ
ツチ素子8はその制御特性により零電圧状態を維
持し、セルB、セルCの状態には変化がない。
At this time, unselected cells B and C are each
Only Ix or Iy' acts, and the switch element 8 of each cell maintains a zero voltage state due to its control characteristics, and the states of cells B and C remain unchanged.

セルAの状態を読み出す方法を示す。 A method for reading the state of cell A will be shown.

セルAに関係した列ライン5及び行ライン7に
それぞれセル電流Iy読み取り電流Ixをそれぞれ電
源10,12から流す。この場合読み取り電流は
書き込み時に行ライン7に流した電流と同じであ
る。もしセルAにIcircが流れていればセルAの
分枝3,4に流れる電流はそれぞれImin,Iy−
Imin=(1−K)Iy+IcircとなりセルAにIcircが
流れていなければセルAの分枝3,4に流れる電
流はそれぞれKIy,(1−K)Iyとなる。その結
果セルAにIcircが流れている場合はその制御特
性によりセルAのスイツチ素子9は電圧状態にス
イツチし、セルAにIcircが流れていない場合に
はセルAのスイツチ素子9は零電圧状態を維持
し、この二つの状態がセルAに関係する検出器1
4によつて弁別される。その後該Iy、該Ixを0と
すれば、読み出し前にIcircが流れていた場合も
Icircが流れていなかつた場合も、どちらの場合
にもセルAの状態はそれぞれ読み出し前の状態を
再現し、非破壊での読み出しが可能となる。
A cell current Iy and read current Ix are applied to the column line 5 and row line 7 associated with cell A, respectively, from power supplies 10 and 12, respectively. In this case, the read current is the same as the current applied to the row line 7 during writing. If Icirc flows in cell A, the currents flowing in branches 3 and 4 of cell A are Imin and Iy−, respectively.
Imin=(1-K)Iy+Icirc, and if Icirc does not flow in cell A, the currents flowing in branches 3 and 4 of cell A will be KIy and (1-K)Iy, respectively. As a result, when Icirc is flowing through cell A, the switch element 9 of cell A is switched to the voltage state due to its control characteristics, and when Icirc is not flowing through cell A, the switch element 9 of cell A is switched to the zero voltage state. , and these two states are related to cell A.
4. After that, if Iy and Ix are set to 0, even if Icirc is flowing before reading,
Even when Icirc is not flowing, in either case, the state of cell A reproduces the state before reading, and non-destructive reading becomes possible.

この時非選択のセルCにはIyが作用するがIy=
0の後には初期の状態を維持し、同セルBにはIx
が作用するが、セルBのスイツチ素子28はその
制御特性により零電圧状態を維持し、セルBの状
態には変化がない。
At this time, Iy acts on the unselected cell C, but Iy=
After 0, the initial state is maintained, and the same cell B has Ix
However, the switch element 28 of cell B maintains a zero voltage state due to its control characteristics, and the state of cell B remains unchanged.

以上実施例につき説明したが本発明の主要部は
読み出しゲートが連結した書き込みゲートの制御
線に流れる電流が書き込み時と読み出し時で同じ
事であり、その結果は書き込みゲートの制御線に
連結して読み出しゲートを配置したジヨセフソン
NDRO記憶回路を駆動できる事にある。
Although the embodiments have been explained above, the main part of the present invention is that the current flowing through the control line of the write gate connected to the read gate is the same during writing and reading, and the result is that the current flowing through the control line of the write gate connected to the read gate is the same during writing and reading. Josephson with readout gate
Its ability to drive the NDRO memory circuit.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来技術を説明する為のジヨセフソン
NDRO記憶回路の2×2アレイを示す図である。
第2図は本発明を説明する為の簡素化されたジヨ
セフソンNDRO記憶回路の一つのセルを示す図
である。第3図a,bはそれぞれ本発明の駆動法
を実現するために第2図のセルに用いられたスイ
ツチ素子の制御特性を示す図である。第4図は本
発明の一実施例を説明するための、ジヨセフソン
NDRO記憶回路の2×2アレイを示す図である。 第1図、第2図、第4図において1は記憶セ
ル、2は超伝導閉ループ、3,4は分枝路、5は
列ライン、6は制御列ライン、7は行ライン、
8,9はスイツチ素子、10,11,12,13
は電源、14は検出器、15は読み出しラインで
ある。
Figure 1 shows Josephson's diagram for explaining the conventional technology.
FIG. 2 shows a 2×2 array of NDRO storage circuits.
FIG. 2 is a diagram illustrating one cell of a simplified Josephson NDRO storage circuit for explaining the present invention. 3a and 3b are diagrams each showing the control characteristics of the switch element used in the cell of FIG. 2 to realize the driving method of the present invention. FIG. 4 shows Josephson's diagram for explaining one embodiment of the present invention.
FIG. 2 shows a 2×2 array of NDRO storage circuits. In FIGS. 1, 2, and 4, 1 is a storage cell, 2 is a superconducting closed loop, 3 and 4 are branch paths, 5 is a column line, 6 is a control column line, 7 is a row line,
8, 9 are switch elements, 10, 11, 12, 13
is a power supply, 14 is a detector, and 15 is a readout line.

Claims (1)

【特許請求の範囲】[Claims] 1 第1の分枝と第2の分枝からなる超伝導閉ル
ープと、上記第1の分枝中に配置されたジヨセフ
ソン電流を流しうる第1のスイツチ素子と、上記
第1のスイツチ素子と電磁的に結合するように配
置された複数の制御線と該制御線の内の少なくと
も一本の制御線と連結し、上記第2の分枝と電磁
的に結合するように配置されたジヨセフソン電流
を流しうる第2のスイツチ素子とからなり、上記
第1のスイツチ素子を書き込みゲートとして用い
て流れの向きの異なる循環電流、あるいは循環電
流の有無として2進情報を上記超伝導閉ループに
貯え、上記第2のスイツチ素子を読み出しゲート
として用いるジヨセフソン記憶回路の駆動に於い
て、上記第2のスイツチ素子が連結した上記第1
の制御線に流れる電流が書き込み時と、読み出し
時とで同じ事を特徴とするジヨセフソン記憶回路
の駆動方法。
1. A superconducting closed loop consisting of a first branch and a second branch, a first switch element arranged in the first branch and capable of flowing Josephson current, and a Josephson current connected to at least one control line among the plurality of control lines arranged to be coupled to each other, and arranged to be electromagnetically coupled to the second branch; The first switch element is used as a write gate to store binary information in the superconducting closed loop as circulating currents having different flow directions or the presence or absence of the circulating current. In driving a Josephson memory circuit using a second switch element as a read gate, the first switch element connected to the second switch element is
A method for driving a Josephson memory circuit characterized in that the current flowing through the control line is the same during writing and during reading.
JP58015660A 1983-02-02 1983-02-02 Driving method of josephson storage circuit Granted JPS59142796A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58015660A JPS59142796A (en) 1983-02-02 1983-02-02 Driving method of josephson storage circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58015660A JPS59142796A (en) 1983-02-02 1983-02-02 Driving method of josephson storage circuit

Publications (2)

Publication Number Publication Date
JPS59142796A JPS59142796A (en) 1984-08-16
JPH0381240B2 true JPH0381240B2 (en) 1991-12-27

Family

ID=11894889

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58015660A Granted JPS59142796A (en) 1983-02-02 1983-02-02 Driving method of josephson storage circuit

Country Status (1)

Country Link
JP (1) JPS59142796A (en)

Also Published As

Publication number Publication date
JPS59142796A (en) 1984-08-16

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