JPH0382151A - MOS type semiconductor integrated circuit - Google Patents
MOS type semiconductor integrated circuitInfo
- Publication number
- JPH0382151A JPH0382151A JP1219427A JP21942789A JPH0382151A JP H0382151 A JPH0382151 A JP H0382151A JP 1219427 A JP1219427 A JP 1219427A JP 21942789 A JP21942789 A JP 21942789A JP H0382151 A JPH0382151 A JP H0382151A
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- Prior art keywords
- circuit
- semiconductor integrated
- type semiconductor
- integrated circuit
- state
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/211—Design considerations for internal polarisation
- H10D89/213—Design considerations for internal polarisation in field-effect devices
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- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
［産業上の利用分野コ
本発明は、ＭＯＳ型半導体集積回路に関し、特に高速で
且つ低消費電力のＭＯＳ型半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS type semiconductor integrated circuit, and more particularly to a MOS type semiconductor integrated circuit that is high speed and has low power consumption.
［従来の技術］
ＭＯＳ型半導体集積回路では、そのしきい値電圧の設定
値を変化させると、次のような回路動作状態の変化があ
る。即ち、ＭＯＳトランジスタのしきい値が大きい場合
には、ＭＯＳトランジスタの駆動電流が減少し、回″蕗
の動作速度が低下する。[Prior Art] In a MOS type semiconductor integrated circuit, when the set value of the threshold voltage is changed, the circuit operating state changes as follows. That is, when the threshold value of the MOS transistor is large, the drive current of the MOS transistor decreases, and the operating speed of the circuit decreases.
これは、飽和領域のドレイン電流がゲート電圧としきい
値電圧の差の２乗にほぼ比例するというＭＯＳトランジ
スタの特性によるものである。一方、ＭＯＳトランジス
タのしきい値が小さい場合には、回路の動作速度は向上
するものの、ゲート・ソース間電圧がＯｖのときに流れ
るサブスレッシロルド電流が増加するため、インバータ
回路及びＮＡＮＤ回路等を構成するＭＯＳトランジスタ
がオフであっても、電源−接地電位間に流れる電流が増
加し、集積回路全体の消費電力が増加する。This is due to the characteristic of the MOS transistor that the drain current in the saturation region is approximately proportional to the square of the difference between the gate voltage and the threshold voltage. On the other hand, when the threshold value of the MOS transistor is small, although the operating speed of the circuit improves, the subthreshold current that flows when the gate-source voltage is Ov increases, so the inverter circuit, NAND circuit, etc. Even if the MOS transistors constituting the integrated circuit are off, the current flowing between the power supply and the ground potential increases, increasing the power consumption of the entire integrated circuit.
このため、従来のＭＯ８半導体集積回路では、高速性と
低消費電力性の両者を考慮してしきい値電圧が設定され
ている。Therefore, in the conventional MO8 semiconductor integrated circuit, the threshold voltage is set in consideration of both high speed and low power consumption.
［発明が解決しようとする課題］
しかしながら、上述した従来のＭＯ８型半導体集積回路
では、しきい値を大きくすると回路の動作速度が低下し
、しきい値を小さくすると回路の消費電力が増すため、
高速性と低消費電力性という半導体集積回路の２つの目
標性能を程々に満足させる程度のしきい値電圧にしか設
定することができず、両性能を共に満足させることが難
しいという問題点があった。[Problems to be Solved by the Invention] However, in the conventional MO8 type semiconductor integrated circuit described above, increasing the threshold value reduces the operating speed of the circuit, and decreasing the threshold value increases the power consumption of the circuit.
The problem is that the threshold voltage can only be set to a level that moderately satisfies the two target performances of semiconductor integrated circuits: high speed and low power consumption, and it is difficult to satisfy both performances. Ta.
本発明はかかる問題点に鑑みてなされたものであって、
高速性に優れ、しかも消費電力が小さいＭＯ８型半導体
集積回路を提供することを目的とする。The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide an MO8 type semiconductor integrated circuit that has excellent high speed performance and low power consumption.
［課題を解決するための手段］
本発明に係るＭＯ３型半導体集積回路は、ＭＯＳトラン
ジスタにて構成され、データが入出力される活性状態と
内部状態のみが保持される待機状態の少なくとも２状態
を有する内部回路と、この内部回路を構成する前記ＭＯ
８）ランジスクに対し前記待機状態で前記活性状態より
も大きなソース・基板開通バイアス電圧を印加する基板
バイアス発生回路とを具備したことを特徴とする。[Means for Solving the Problems] The MO3 type semiconductor integrated circuit according to the present invention is composed of MOS transistors and has at least two states: an active state in which data is input/output and a standby state in which only the internal state is held. an internal circuit having a
8) The present invention is characterized by comprising a substrate bias generation circuit that applies a source/substrate opening bias voltage larger than that in the active state to the transistor in the standby state.
また、ＭＯＳトランジスタがＰ型又はＮ型半導体ウェル
中に形成されている場合には、上記ソース・基板間逆バ
イアス電圧を印加する基板バイアス発生回路の代わりに
ソース・ウェル間逆バイアス電圧を印加するウェルバイ
アス発生回路が設けられる。Furthermore, when the MOS transistor is formed in a P-type or N-type semiconductor well, a source-well reverse bias voltage is applied instead of the substrate bias generation circuit that applies the source-substrate reverse bias voltage. A well bias generation circuit is provided.
［作用］
本発明によれば、内部回路が待機状態のときには、活゛
性状態のときよりも大きなソース・基板間違バイアス？
Ｉｔ圧又はソース・ウェル間逆バイアス電圧が印加され
る。このため、内部回路が待機状態のときには、基板又
はウェルに印加される逆バイアス電圧が大きいので、ト
ランジスタのしきい値が大きくなり、トランジスタの駆
動電流が減少する。一方、内部回路が活性状態のときに
は、基板又はウェルに印加される逆バイアス電圧が小さ
くなるので、トランジスタのしきい値が低下し、トラン
ジスタの駆動電流が増大・する。このため、トランジス
タの動作速度が向上する。[Operation] According to the present invention, when the internal circuit is in the standby state, the source/substrate misbias is larger than when it is in the active state.
It pressure or source-well reverse bias voltage is applied. Therefore, when the internal circuit is in a standby state, the reverse bias voltage applied to the substrate or well is large, so the threshold value of the transistor becomes large and the drive current of the transistor decreases. On the other hand, when the internal circuit is in an active state, the reverse bias voltage applied to the substrate or well becomes smaller, so the threshold value of the transistor decreases and the drive current of the transistor increases. Therefore, the operating speed of the transistor is improved.
このように、本発咀によれば、内部回路が待機状態であ
るか活性状態であるかによって、基板又はウェルの逆バ
イアス電圧を変化させることにより、待機状態では消費
電力を抑制し、活性状態では動作速度を向上させるよう
にしているので、全体として高速性及び低消費電力性を
高めることができる。In this way, according to the present invention, by changing the reverse bias voltage of the substrate or well depending on whether the internal circuit is in the standby state or the active state, power consumption can be suppressed in the standby state, and power consumption can be reduced in the active state. Since the operation speed is improved, overall high speed and low power consumption can be achieved.
［実施例コ
以下、添付の図面を参照しながら本発明の実施例につい
て説明する。[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
第１図は本発明の第１の実施例に係るＭＯ８型半導体集
積回路のブロック図である。FIG. 1 is a block diagram of an MO8 type semiconductor integrated circuit according to a first embodiment of the present invention.
ＭＯ８型半導体集積回路１の内部には、内部回路２と基
板バイアス発生回路３とが設けられている。内部回路２
は、例えばＣＭＯＳインバータ回路からなる入出力回路
等から構成されており、集積回路ｌの外部に引き出され
たデータＩ１０端子４に接続されたものとなっている。Inside the MO8 type semiconductor integrated circuit 1, an internal circuit 2 and a substrate bias generation circuit 3 are provided. Internal circuit 2
is composed of an input/output circuit made of, for example, a CMOS inverter circuit, and is connected to a data I10 terminal 4 drawn out to the outside of the integrated circuit l.
基板バイアス発生回路３は、内部回路２の内部状態に応
じて異なる基板バイアス電圧を発生させるもので、チ・
ノブセレクト端子５によって、その発生バイアス電圧が
制御されるものとなっている。即ち、この基板バイアス
発生回路３は、例えば内部回路２を構成するＮチャネル
ＭＯＳトランジスタのソース電位がＯＶであるとすると
、このトランジスタが形成されたＰ型半導体基板に、活
性状態ではＯｖの基板バイアスが、また、待機状態では
一３Ｖの基板バイアスが印加されるように、Ｏｖ及び−
３Ｖの基板バイアスを発生する。The substrate bias generation circuit 3 generates different substrate bias voltages depending on the internal state of the internal circuit 2.
The generated bias voltage is controlled by the knob select terminal 5. That is, if the source potential of the N-channel MOS transistor constituting the internal circuit 2 is OV, the substrate bias generation circuit 3 applies a substrate bias of Ov to the P-type semiconductor substrate on which this transistor is formed in the active state. However, in the standby state, Ov and -3V are applied so that a substrate bias of -3V is applied.
Generates a 3V substrate bias.
次に、このように構成されたＭＯ８型半導体集積回路の
動作について説明する。Next, the operation of the MO8 type semiconductor integrated circuit configured as described above will be explained.
第２図は、ＮチャネルＭＯＳトランジスタの基板バイア
スとしてＯｖと一３Ｖを夫々印加した場合のドレイン電
圧に対するドレイン電流を、また、第３図は同じくゲー
ト電圧に対するドレイン電流を夫々示した図である。基
板バイアスがＯＶのときには、トランジスタのしきい値
電圧が、例えばＯｖから０．５Ｖと低いので、トランジ
スタの駆動電流が大きくなる。これに対し、基板バイア
スが一３Ｖのときには、トランジスタのしきい値電圧が
、例えば０．５Ｖから１．ＯＶと上昇するので、トラン
ジスタの駆動電流が小さくなる。FIG. 2 is a diagram showing drain current versus drain voltage when Ov and -3V are applied as substrate biases of an N-channel MOS transistor, and FIG. 3 is a diagram showing drain current versus gate voltage. When the substrate bias is OV, the threshold voltage of the transistor is low, for example 0.5V from Ov, so the drive current of the transistor becomes large. On the other hand, when the substrate bias is 13V, the threshold voltage of the transistor varies from 0.5V to 1.5V, for example. Since the voltage increases to OV, the drive current of the transistor becomes smaller.
本実施例においては、内部回路２が活性状態のとき、つ
まりチップセレクト端子５がイネーブル状態になったと
き、基板バイアス発生回路３からＯｖの基板バイアスが
出力されるので、ドレイン電流が増して内部回路２のＮ
チャネルＭＯＳトランジスタの動作を高速にすることが
できる。この場合、第３図に示すように、ゲート電圧が
ＯＶでも、１Ｏ−１０Ａ程度のサブスレッシロルド電流
が流れてしまう。しかしながら、このとき内部回路２は
活性状態であり、充放電電流が大きいため、サブスレッ
シロルド電流による消費電流の増大の影響は非常に小さ
い。In this embodiment, when the internal circuit 2 is active, that is, when the chip select terminal 5 is enabled, the substrate bias generation circuit 3 outputs a substrate bias of Ov, so that the drain current increases and the internal N of circuit 2
The operation of the channel MOS transistor can be made faster. In this case, as shown in FIG. 3, even if the gate voltage is OV, a subthreshold current of about 10-10 A flows. However, at this time, the internal circuit 2 is in an active state and the charging/discharging current is large, so the influence of the increase in current consumption due to the subthreshold current is very small.
また、内部回路２が待機状態のとき、つまりチップセレ
クト端子５がディスエーブル状態になったとき、基板バ
イアス発生回路３から一３ｖの基板バイアスが出力され
るので、内部回路２のサブスレッシ日ルド電流を１Ｏ−
１２Ａ以下にすることができる。このため、待機状態で
の消費電力を十分に小さくすることができる。この場合
、トランジスタの動作速度は低下するが、待機状態であ
るため、内部回路は動作しないので、なんら問題はない
。Furthermore, when the internal circuit 2 is in a standby state, that is, when the chip select terminal 5 is in a disabled state, a substrate bias of -3V is output from the substrate bias generation circuit 3, so that the subthreshold current of the internal circuit 2 is 1O-
It can be made 12A or less. Therefore, power consumption in the standby state can be sufficiently reduced. In this case, although the operating speed of the transistor decreases, there is no problem because the internal circuit does not operate because it is in a standby state.
このように、本実施例の回路によれば、活性状態時のし
きい値電圧を低くして高速の回路動作を実現すると共に
、待機状態時のサブスレッシロルド電流の低減により、
従来に比べ、３桁程度待機状態での消費電力を低減する
ことができる。As described above, according to the circuit of this embodiment, high-speed circuit operation is realized by lowering the threshold voltage in the active state, and by reducing the subthreshold current in the standby state,
Compared to the conventional technology, power consumption in the standby state can be reduced by about three orders of magnitude.
なお、上記基板バイアス発生回路３は、特に待機状態で
絶対値的に大きな基板バイアス値を発生するので、その
際の消費電力が問題となるが、待機状態では内部回路２
が動作しないので、基板バイアス発生回路３の負荷は極
めて小さい。このため、基板バイアス発生回路３を動作
させることによる消費電力の増大は殆ど無視することが
できる。Note that the substrate bias generation circuit 3 generates a substrate bias value that is particularly large in absolute value in the standby state, so power consumption at that time becomes a problem, but in the standby state the internal circuit 2
does not operate, the load on the substrate bias generation circuit 3 is extremely small. Therefore, the increase in power consumption due to operating the substrate bias generation circuit 3 can be almost ignored.
ところで、ＭＯ８型半導体集積回路は、年々その素子寸
法が縮小され、より高集積化されている。Incidentally, MO8 type semiconductor integrated circuits are becoming more and more highly integrated as their element dimensions are reduced year by year.
そのため、ゲート酸化膜の膜厚が１０ｎｍ以下のものも
作られるようになってきた。この場合、ゲート酸化膜の
耐圧も低下するので、信頼性確保のために電源電圧を従
来の５Ｖから３Ｖ程度に低下させる必要がある。ところ
が、前述したように、ＭＯＳトランジスタの飽和領域の
ドレイン電流は、ゲートｍ圧としきい値電圧の差の２乗
にほぼ比例する。よって、しきい値電圧を一定にすると
、電源電圧がしきい値電圧に近付いた場合、ドレイン電
流は急激に小さくなり、回路速度が極端に低下する。Therefore, gate oxide films with a thickness of 10 nm or less have come to be manufactured. In this case, the withstand voltage of the gate oxide film also decreases, so it is necessary to lower the power supply voltage from the conventional 5V to about 3V to ensure reliability. However, as described above, the drain current in the saturation region of the MOS transistor is approximately proportional to the square of the difference between the gate m voltage and the threshold voltage. Therefore, when the threshold voltage is kept constant, when the power supply voltage approaches the threshold voltage, the drain current decreases rapidly and the circuit speed decreases extremely.
この点、第１図に示したＭＯ８型半導体集積回路によれ
ば、活性状態でしきい値電圧を小さくすることができる
ので、従来に比べ、より低い電源電圧まで急激なドレイ
ン電流の減少が起こらず、極端な回路速度の低下を防ぐ
ことができる。In this regard, according to the MO8 type semiconductor integrated circuit shown in FIG. 1, the threshold voltage can be lowered in the active state, so a sudden decrease in drain current does not occur even at a lower power supply voltage than in the past. First, it is possible to prevent an extreme decrease in circuit speed.
第４図は本発明の第２の実施例に係るＭＯ８型半導体集
積回路の構成を示すブロック図である。FIG. 4 is a block diagram showing the configuration of an MO8 type semiconductor integrated circuit according to a second embodiment of the present invention.
ＭＯ３型半導体集積回路１１の内部には、第１の内部回
路１２と、第２の内部回路１３と、基板バイアス発生回
路１４とが設けられている。第１の内部回路１２と第２
の内部回路１３には、夫々データＩ１０端子１５．１６
が接続されている。Inside the MO3 type semiconductor integrated circuit 11, a first internal circuit 12, a second internal circuit 13, and a substrate bias generation circuit 14 are provided. The first internal circuit 12 and the second internal circuit
The internal circuit 13 includes data I10 terminals 15 and 16, respectively.
is connected.
また、第１の内部回路１２と第２の内部回路１３とは、
その基板又はウェルが互いに分離されており、それらの
間はデータの送受信が行えるように接続されている。基
板バイアス発生回路１４は、活性状態・待機状態選択端
子１７に入力される信号に応じて２種類の基板バイアス
電圧を発生させる。Furthermore, the first internal circuit 12 and the second internal circuit 13 are
The substrates or wells are separated from each other and connected so that data can be sent and received. The substrate bias generation circuit 14 generates two types of substrate bias voltages according to the signal input to the active state/standby state selection terminal 17.
この回路では、第１の内部回路１２はチップ内で特に高
速動作を要求され、第２の内部回路１３は比較的低速の
回路動作でもよいとすると、基板バイアス発生回路１４
は、第１の内部回路１２に対してだけ、その待機時に絶
対値的に大きな基板バイアス電圧を発生させる。In this circuit, the first internal circuit 12 is required to operate at a particularly high speed within the chip, and the second internal circuit 13 may operate at a relatively low speed.
generates a substrate bias voltage that is large in absolute value only for the first internal circuit 12 during its standby period.
この回路によれば、内部回路全体に対して基板バイアス
を切り替える場合に比べ、ＭＯＳトランジスタのサブス
レッシミルド電流を小さくすることができるので、活性
状態での消費電力を、より低減することができる。According to this circuit, the subthreshold current of the MOS transistor can be made smaller than when switching the substrate bias for the entire internal circuit, so power consumption in the active state can be further reduced. .
なお、上記の各実施例では、基板バイアス発生回路を使
用したが、制御すべきＮ型又はＰ型ＭＯＳトランジスタ
がＰ型又はＮ型ウェルに形成されている場合には、この
Ｐ型又はＮ型ウェルに対して逆バイアス電圧を発生させ
る回路が使用される。Although the substrate bias generation circuit is used in each of the above embodiments, if the N-type or P-type MOS transistor to be controlled is formed in a P-type or N-type well, this P-type or N-type MOS transistor A circuit is used to generate a reverse bias voltage to the well.
そして、この場合にも本発明の効果を奏することは言う
までもない。It goes without saying that the effects of the present invention can also be achieved in this case.
［発明の効果コ
以上述べたように、本発明は内部回路が活性状態である
場合と、待機状態である場合とで、その基板又はウェル
バイアスを適応的に変化させるようにしたので、活性状
態では高速の回路動作を実現すると共に、待機状態では
消費電力の低減を図ることができ、全体として高速で、
且つ低消費電力のＭＯＳ型半導体集積回路を提供するこ
とができる。[Effects of the Invention] As described above, the present invention adaptively changes the substrate or well bias depending on whether the internal circuit is in the active state or in the standby state. In addition to realizing high-speed circuit operation, it is possible to reduce power consumption in the standby state, and the overall speed is high.
Moreover, a MOS type semiconductor integrated circuit with low power consumption can be provided.
第１図は本発明の第１の実施例に係るＭＯＳ型半導体集
積回路のブロック図、第２図はＭＯＳトランジスタのド
レイン電流の特性図、第３図はＭＯＳトランジスタのサ
ブスレッシロルド電流の特性図、第４図は本発明の第２
の実施例に係るＭＯＳ型半導体集積回路のブロック図で
ある。FIG. 1 is a block diagram of a MOS semiconductor integrated circuit according to the first embodiment of the present invention, FIG. 2 is a characteristic diagram of drain current of a MOS transistor, and FIG. 3 is a characteristic diagram of subthreshold current of a MOS transistor. Figure 4 shows the second embodiment of the present invention.
FIG. 2 is a block diagram of a MOS semiconductor integrated circuit according to an embodiment of the present invention.
Claims (2)
力される活性状態と内部状態のみが保持される待機状態
の少なくとも２状態を有する内部回路と、この内部回路
を構成する前記ＭＯＳトランジスタに対し前記待機状態
で前記活性状態よりも大きなソース・基板間逆バイアス
電圧を印加する基板バイアス発生回路とを具備したこと
を特徴とするＭＯＳ型半導体集積回路。(1) An internal circuit composed of MOS transistors and having at least two states: an active state in which data is input/output and a standby state in which only the internal state is held; 1. A MOS type semiconductor integrated circuit comprising: a substrate bias generation circuit that applies a source-to-substrate reverse bias voltage larger in a standby state than in the active state.
力される活性状態と内部状態のみが保持される待機状態
の少なくとも２状態を有する内部回路と、この内部回路
を構成する前記ＭＯＳトランジスタに対し前記待機状態
で前記活性状態よりも大きなソース・ウェル間逆バイア
ス電圧を印加するウェルバイアス発生回路とを具備した
ことを特徴とするＭＯＳ型半導体集積回路。(2) an internal circuit composed of MOS transistors and having at least two states, an active state in which data is input/output and a standby state in which only the internal state is held; 1. A MOS type semiconductor integrated circuit comprising: a well bias generation circuit that applies a reverse bias voltage between the source and the well that is larger in a standby state than in the active state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01219427A JP3105512B2 (en) | 1989-08-25 | 1989-08-25 | MOS type semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01219427A JP3105512B2 (en) | 1989-08-25 | 1989-08-25 | MOS type semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0382151A true JPH0382151A (en) | 1991-04-08 |
| JP3105512B2 JP3105512B2 (en) | 2000-11-06 |
Family
ID=16735227
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP01219427A Expired - Lifetime JP3105512B2 (en) | 1989-08-25 | 1989-08-25 | MOS type semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3105512B2 (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5672995A (en) * | 1993-11-15 | 1997-09-30 | Matsushita Electric Industrial Co., Ltd. | High speed mis-type intergrated circuit with self-regulated back bias |
| EP0739097A3 (en) * | 1995-04-21 | 1998-01-07 | Nippon Telegraph And Telephone Corporation | MOSFET circuit and CMOS logic circuit using the same |
| US5744996A (en) * | 1992-07-01 | 1998-04-28 | International Business Machines Corporation | CMOS integrated semiconductor circuit |
| US5914515A (en) * | 1994-07-08 | 1999-06-22 | Nippondenso Co., Ltd | Semiconductor device |
| US5990521A (en) * | 1995-08-16 | 1999-11-23 | Nec Corporation | Semiconductor device and method of producing the same |
| US6124752A (en) * | 1996-04-02 | 2000-09-26 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device controlling the threshold value thereof for power reduction at standby mode |
| US6630717B2 (en) | 2000-05-02 | 2003-10-07 | Sharp Kabushiki Kaisha | CMOS semiconductor circuit with reverse bias applied for reduced power consumption |
| US6774440B1 (en) | 1997-05-30 | 2004-08-10 | Sharp Kabushiki Kaisha | Semiconductor device and method for driving the same |
| US6795328B2 (en) | 2002-05-29 | 2004-09-21 | Fujitsu Limited | Semiconductor memory device |
| US7109558B2 (en) | 2001-06-06 | 2006-09-19 | Denso Corporation | Power MOS transistor having capability for setting substrate potential independently of source potential |
| WO2013018217A1 (en) * | 2011-08-03 | 2013-02-07 | 富士通株式会社 | Semiconductor integrated circuit and method for driving latch circuit |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004165649A (en) | 2002-10-21 | 2004-06-10 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
-
1989
- 1989-08-25 JP JP01219427A patent/JP3105512B2/en not_active Expired - Lifetime
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5744996A (en) * | 1992-07-01 | 1998-04-28 | International Business Machines Corporation | CMOS integrated semiconductor circuit |
| US5672995A (en) * | 1993-11-15 | 1997-09-30 | Matsushita Electric Industrial Co., Ltd. | High speed mis-type intergrated circuit with self-regulated back bias |
| US5914515A (en) * | 1994-07-08 | 1999-06-22 | Nippondenso Co., Ltd | Semiconductor device |
| EP0739097A3 (en) * | 1995-04-21 | 1998-01-07 | Nippon Telegraph And Telephone Corporation | MOSFET circuit and CMOS logic circuit using the same |
| US6147386A (en) * | 1995-08-16 | 2000-11-14 | Nec Corporation | Semiconductor device and method of producing the same |
| US5990521A (en) * | 1995-08-16 | 1999-11-23 | Nec Corporation | Semiconductor device and method of producing the same |
| US6124752A (en) * | 1996-04-02 | 2000-09-26 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device controlling the threshold value thereof for power reduction at standby mode |
| US6373323B2 (en) | 1996-04-02 | 2002-04-16 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device with threshold control |
| US6593800B2 (en) | 1996-04-02 | 2003-07-15 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device |
| US6774440B1 (en) | 1997-05-30 | 2004-08-10 | Sharp Kabushiki Kaisha | Semiconductor device and method for driving the same |
| US6630717B2 (en) | 2000-05-02 | 2003-10-07 | Sharp Kabushiki Kaisha | CMOS semiconductor circuit with reverse bias applied for reduced power consumption |
| US7109558B2 (en) | 2001-06-06 | 2006-09-19 | Denso Corporation | Power MOS transistor having capability for setting substrate potential independently of source potential |
| US6795328B2 (en) | 2002-05-29 | 2004-09-21 | Fujitsu Limited | Semiconductor memory device |
| WO2013018217A1 (en) * | 2011-08-03 | 2013-02-07 | 富士通株式会社 | Semiconductor integrated circuit and method for driving latch circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3105512B2 (en) | 2000-11-06 |
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