JPH038318A - Formation of resist pattern - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] 1. The present invention relates to a method for forming a resist pattern formed in a photolithography process in a semiconductor device manufacturing process, and particularly a method for mask alignment and overlay accuracy inspection after mask alignment. The present invention relates to a method of forming a resist pattern.

In general, in the manufacturing process of semiconductor devices, the process of forming a complex circuit pattern consisting of multiple layers includes multiple photolithography processes.

That is, in manufacturing this type of semiconductor device, a resist pattern is formed while controlling the position of a pattern formed on a wafer and another pattern formed in the next process, and then a predetermined etching is performed to form a circuit pattern. will continue to form.

Methods for performing the position control include alignment mainly by mask alignment and overlay accuracy inspection performed after mask alignment.

Mask alignment refers to relatively aligning patterns that have already been formed on the wafer and alignment marks formed on the mask that will be used in the next process, and then
This refers to the process of exposing to light, and by performing development after exposure, a resist pattern of a predetermined shape is formed on the wafer.

Conventionally, this mask alignment has been carried out by utilizing a vernier method, which is mainly used in the inspection process described later, or by an alignment mark method.

In the vernier method, as shown in FIG. 9, mask alignment is performed using what is called a vernier set, which is composed of a main scale 51 and a vernier scale 52. That is, in mask alignment using this vernier method, a first mask on which the main square 51 is formed is transferred onto a wafer as a positioning mark to form a pattern. This main scale 51 is formed into a comb blade shape with a constant pitch T1, and has a scale in the longitudinal direction (indicated by arrow d).

Next, a mask on which a comb-like vernier scale 52 is formed is placed so as to interlock with the main scale 51 on the pattern. This vernier measure 52 has a constant pitch T different from that of the main measure 51, and, like the main measure 51, is graduated in the longitudinal direction (direction of arrow d). Then, move the vernier 52 in the direction of arrow d and search for a place where the scale of the main scale 51 and the scale of the vernier 52 match.0 For example, in this FIG. The 52 scales coincide with the scale rOJ. After this, the left and right gaps 1+ and 1g between the main scale 51 and the vernier scale 52 are measured.

And 1. =1. In this case, the pattern deviation is "O", and exposure and development are performed to form a predetermined pattern. Further, even when t≠t2, if the "deviation" is within an allowable range with respect to the design value, exposure and development are performed to form a predetermined pattern. On the other hand, if t, ≠ t2, and the "deviation" is outside the allowable range with respect to the design value, move the vernier 52 in the direction of arrow d to bring the "deviation" within the allowable range, and then perform the exposure. Developing is performed to form a predetermined pattern.

In addition, the alignment mark method refers to, for example, forming a plurality of alignment patterns having a substantially cross shape on the wafer surface, and then using a mask on which alignment marks having the same shape as the alignment patterns are formed. , mask alignment is performed by arranging the pattern to be aligned and the alignment mark so as to overlap with each other.

Recently, a so-called reduction projection exposure method has been developed in place of the above-mentioned contact exposure method. The reduction projection exposure method exposes each chip on the wafer while performing reduction projection, thereby achieving high resolution.

After mask alignment is performed and a pattern is formed by exposure and development, an overlay accuracy inspection is generally performed to inspect the accuracy of mask alignment. That is, in the resist patterns formed by the first mask and the second mask, the amount of deviation due to overlapping of the patterns is inspected.

In the case of a contact exposure method, exposure is performed by bringing a wafer on which a pattern is formed into close contact with a mask. When mask alignment is performed using conventional alignment marks, the accuracy tends to be lower than when mask alignment is performed using the vernier method. need to be determined.

Furthermore, in the reduction projection exposure method, since exposure is carried out one chip at a time, overlay accuracy inspection after mask alignment is one of the important inspection items.

As described above, the results of overlay accuracy inspection, along with line width control, greatly influence the design of semiconductor elements, and are incorporated into the design rules for device design.

Conventionally, as this type of inspection method, a method of carrying out an inspection using the above-mentioned Banya method, a method of carrying out a pattern inspection on an actual device, etc. are known.

In the vernier inspection method, in the case of a contact exposure method, mask alignment using a vernier is performed by the method described above.

In the case of the reduction projection exposure method, alignment marks are specified for each device, so it is not possible to align the mask with a vernier. When inspection is performed using a pattern (vernier), that is, when the pattern to be aligned and the alignment pattern are already formed on the wafer, the amount of "deviation" in the overlapping of the scales is permissible from the design value. If it is within the range, the inspection will be passed; if it is outside the allowable range with respect to the design value, the inspection will be failed. If the inspection fails, the patterned resist is peeled off using a sulfuric acid boiler, etc., the resist is applied again, the mask is aligned, the resist pattern is formed by exposure and development, and the "misalignment" of the overlay is reapplied. ” and determines whether the resist pattern is acceptable or not. This process is then repeated until the amount of "misalignment" falls within the allowable range to form a desired resist pattern.

Furthermore, even when mask alignment is performed using conventional alignment marks in a contact exposure method, overlay accuracy inspection can be similarly performed using the vernier method. That is, after a vernier pattern consisting of the main scale 51 and the vernier scale 52 is formed on the wafer, the same inspection as described above is performed.

Furthermore, pattern inspection on an actual device is to visually identify locations on the actual device that require strict overlay accuracy, and to determine whether or not the overlapping patterns are acceptable in terms of design.

In addition, as another means of inspecting overlay accuracy,
A method of combining parallel line segments and oblique line segments that have an inclination angle with respect to the parallel line segments has also been proposed (Japanese Patent Laid-Open No. 60-3
Publication No. 0135).

The conventional mask alignment method described above has the following problems.

■In mask alignment using the vernier method, the vernier set occupies a large area, so in order to increase the number of multipliers within the wafer of semiconductor devices to be manufactured, the vernier set is placed in the so-called TEG area (Test Element
t Group Area) or on the scrub line.

However, even when placing the vernier set in the TEG area, it takes up a large area, so not all overlapping patterns can be placed in the TEG area, and TEG chips are placed on the wafer. In this case, there is a limit to the number of wafers that can be arranged, making it difficult to achieve perfect alignment to every corner of the wafer.

Furthermore, if a vernier set is placed in the scrub line, there is a possibility that the vernier set will peel off from the wafer during the manufacturing process (especially during dry etching), causing dust to be generated and reducing the yield of semiconductor device manufacturing. There is a possibility.

In addition, mask alignment must be performed in both the X-axis direction and the Y-axis direction, but in the vernier method, the X-axis direction and the Y-axis direction are performed separately, so the throughput (
processing capacity) is poor.

■When performing mask alignment using alignment marks in the contact exposure method, it is difficult to form a desired resist pattern by aligning the mask twice because the marks for "alignment" are generally simple. , it is easy to fail in the inspection process, often resulting in the need to redo mask alignment.

In view of these problems, the first object of the present invention is to provide a method for forming a resist pattern that includes a mask alignment step that allows rapid and highly accurate mask alignment using a simple and inexpensive method. .

Furthermore, conventional overlay accuracy inspections have the following problems.

■If inspection is performed using the vernier method, the same problems as the above-mentioned mask alignment will occur.

In addition, in overlay accuracy inspection, it is necessary to inspect both the X-axis direction and the Y-axis direction, and the vernier method, which inspects the X-axis direction and Y-axis direction separately, takes too much time. , throughput is poor.

■In the method of pattern inspection on the actual device, the overlay accuracy of patterns that have already been formed is inspected, which requires a high degree of skill and is inefficient and reduces production efficiency. .

■In the method disclosed in Japanese Patent Application Laid-open No. 60-30135 mentioned above, when the thickness of the resist changes or the step of the alignment mark changes, the line width changes.
Accurate judgment of overlay is essential, and the practicality of forming lines diagonal to the X-Y axis is questionable considering the commonly used control of the movement direction of the electron beam (X-Y control). be. Moreover, this diagonal line lacks sharpness because the edges appear step-like.

As described above, even with the method disclosed in this publication, it is difficult to accurately test the overlay accuracy, and a faster and more accurate method for testing the overlay accuracy is desired.

In view of these problems, the present invention aims to provide a resist pattern forming method that can form a designed resist pattern on a wafer while performing overlay inspection in an accurate and easy manner. 2 objectives.

In order to achieve the above-mentioned first object, a method for forming a resist pattern according to the present invention includes a first mask on which alignment marks are formed and a second mask on which alignment marks are formed. A method for forming a resist pattern in which a pattern is repeatedly formed on a wafer using a mask while performing mask alignment, wherein the mark for alignment and the mark for alignment are both formed in a square shape. and a center line parallel to a pair of opposing sides of the outer frame, and the center line of the mark to be aligned and the center line of the alignment mark are orthogonal to each other. After forming the respective marks on the first and second masks and forming a pattern on a wafer using the first mask, a resist is applied on the pattern, and then a resist is applied on the pattern. The method is characterized in that a resist pattern is formed while performing alignment with a pattern for alignment formed based on the mark for alignment using a mask.

Further, in the above forming method, the mark for alignment and the alignment mark in which a part of the square outer frame is missing are formed on the first and second masks, and the first and second masks Alignment may also be performed using .

Furthermore, in order to achieve the above-mentioned second object, the method for forming a resist pattern according to the present invention includes the above-mentioned first and second methods.
A resist pattern forming method in which a resist pattern is formed while inspecting the overlay accuracy of the resist pattern using a first mask, the method comprising: forming a pattern on a wafer using the first mask; Applying a resist on the pattern, then forming a pattern on the resist using the second mask, and then applying the first mask to the resist.
The registration accuracy of the alignment pattern formed based on the alignment mark of the second mask and the alignment pattern formed based on the alignment mark of the second mask is inspected. It is characterized by determining the pass/fail of a pattern.

Further, in the above forming method, the mark for alignment and the alignment mark in which a part of the square outer frame is missing are formed on the first and second masks, and the first and second masks may be used to determine pass/fail of the resist pattern.

In the present invention, the so-called mask patterns formed on the mask are called marks, that is, alignment marks, alignment marks, etc., and these marks are transferred and formed onto the wafer. pattern things
・In other words, they are called a pattern for alignment, a pattern for alignment, etc. Further, it goes without saying that the pattern for alignment and the pattern for alignment do not mean a circuit pattern.

According to the method for forming a resist pattern according to the first object, both the alignment mark and the alignment mark are formed by forming an outer frame formed in a square shape and a pair of opposing edges of the outer frame. forming the mark on each of the first and second masks so that the mark is formed of a center line parallel to the side, and the center line of the mark to be aligned and the center line of the alignment mark are orthogonal to each other; Therefore, if the second mask is arranged in such a manner that the center line of the alignment pattern formed based on the alignment mark and the center line of the alignment mark are orthogonal to each other. ,
The correlation between the pattern for alignment and the alignment mark has a substantially grid shape in plan view.

Therefore, by measuring the distance between the outer frame and the center line, it is possible to simultaneously measure the amount of deviation in the X-axis direction and the Y-axis direction. Then, after moving the second mask to bring the amount of deviation due to overlapping within an allowable range with respect to the design value, exposure and development are performed to form a desired resist pattern.

In addition, when using a positioning mark with a part of the square outer frame missing and first and second masks on which the positioning mark is formed, the positioning mark transferred onto the wafer may be When the second mask is placed over the alignment pattern so that the alignment pattern and the alignment mark are perpendicular to each other, the correlation between the alignment pattern and the alignment mark is It becomes like this. In this case, as described above, by measuring the gap between the outer frame and the center line, the amount of deviation in the X-axis direction and the Y-axis direction can be determined at the same time. Furthermore, since it is possible to prevent the outer frame of the pattern for alignment and the outer frame of the alignment mark from overlapping, "misalignment" due to interference between the line widths of these outer frames does not occur.

According to the resist pattern forming method according to the second object, these patterns are formed on the wafer based on the alignment marks and alignment marks of the first and second masks used for the mask alignment. Therefore, in the overlay accuracy inspection, by measuring the distance between the outer frame and the center line, the amount of deviation in the X-axis direction and the Y-axis direction can be determined at the same time, and the pass/fail of the inspection is determined.

In addition, there are also a mark for alignment whose square outer frame is partially missing and a first mark on which a mark for alignment is formed.
Even when a second mask is used, if it is arranged and exposed and developed in the same manner as in the case of mask alignment described above, the correlation between the pattern to be aligned and the pattern for alignment will be on a planar perspective. Become. In this case as well, by measuring the distance between the outer frame and the intermediate flame wire, the amount of deviation in the X-axis direction and the Y-axis direction can be determined at the same time, and the pass/fail of the inspection is determined. Also, in this case, as in the case of mask alignment, it is possible to prevent the outer frame of the pattern to be aligned and the outer frame of the alignment pattern from overlapping each other, and the interference between the line widths of these outer frames can be prevented. No "misalignment" occurs.

1 ri] Hereinafter, embodiments of the present invention will be explained in detail based on the drawings.

In FIG. 2, reference numeral 1a indicates an example of a mark for alignment formed on the first mask, and the mark for alignment la includes an outer frame 2a formed in a square shape, It is composed of a pair of opposing sides 3a of the outer frame 2a, and a center line 4a parallel to 3a.

Further, in FIG. 3, reference numeral 5a indicates an example of an alignment mark formed on the second mask, and this alignment mark 5a also has a square shape like the alignment target mark 1a. and a center line 8 parallel to a pair of opposing sides 7a, 7a of the outer frame 6a.
It is composed of a. Furthermore, this center line 8a is
It is formed on the second mask in a form perpendicular to the center line 4a of the alignment mark la.

Next, a method of performing mask alignment using the first mask and the second mask to form a resist pattern on a wafer will be described.

First, the first mask is placed over a wafer coated with resist, and exposed and developed to form a pattern.

Next, after applying a resist on the pattern, a first
As shown in the figure, the center line 4b of the alignment pattern lb formed by transferring the alignment mark 1a onto the wafer and the center of the alignment mark 5a formed on the second mask. The second mask is arranged so that the lines 8a are orthogonal to each other. That is, when the alignment pattern lb floating on the resist and the alignment mark 5a are superimposed, the correlation between the alignment mark 5a and the alignment pattern lb is approximately a lattice in plan view. The second mask is arranged so as to form a shape. In this case, the second mask and the wafer are parallel to each other and spaced apart from each other by about several tens of micrometers.

Next, the degree of overlap between the alignment target pattern 1b and the alignment mark 5a is enlarged using a microscope, and the distance a1 between the four outer frames 2b, 6a and the center lines 4b, 8a,
Measure a,,al,a4. That is, the interval a,
By measuring ~a4, the amount of deviation from the design value due to the overlapping of the X-axis direction and the Y-axis direction can be found simultaneously in the X-axis direction and the Y-axis direction.

When the amount of deviation is within the allowable range with respect to the design value, the mask described in Subscript 2 is brought into close contact with the wafer, and exposure and development are performed to form a resist pattern on the wafer. In addition, if this amount of deviation is outside the allowable range with respect to the design value, move the second mask in the X-axis direction and/or Y-axis direction to adjust the distances a, ~a4 to the allowable range with respect to the design value. After that, the second mask and the wafer are brought into close contact with each other, and exposure and development are performed to form a predetermined resist pattern on the wafer. That is, the alignment mark 5a is transferred to the wafer to form the alignment pattern 5b, and a predetermined resist pattern is also formed on the wafer.

As described above, in the resist pattern forming method according to this embodiment, mask alignment is performed by arranging the second mask so that the pattern to be aligned lb and the alignment mark 5a form a substantially grid shape in plan view. As a result, accuracy is significantly improved compared to the conventional method using alignment marks.
Furthermore, compared to the vernier method (see Figure 9), the pattern for mask alignment is smaller, and
Mask alignment in the axial direction can be performed simultaneously, and the time required for mask alignment can be shortened.

FIGS. 4 to 6 show a mask alignment method according to a second embodiment, in which the square outer frames 2a and 6a of the first embodiment are partially missing. It has become.

That is, FIG. 4 shows the alignment mark 10a formed on the first mask, and FIG. 5 shows the alignment mark 11a formed on the second mask. Both the alignment mark 10a and the alignment mark lla are formed into a substantially chair shape.

When performing mask alignment using the first and second masks on which such alignment marks loa and alignment marks lla are formed, first, as shown in FIG. After transferring the alignment mark loa onto the wafer to form an alignment pattern 10b and applying a resist thereon, the center line 4b of the alignment pattern lOb and After arranging the second mask so that the center line 8a of the alignment mark lla is perpendicular to the center line 8a so as to be on the plane view, the intervals b1 to b between the outer frame 2b%6a and the center lines 4b and 8a are determined. By measuring, as in the first embodiment, the amount of deviation due to overlapping in the X-axis direction and Y-axis direction is controlled, and then exposure and development are performed to form a predetermined resist pattern.

Fig. 7 shows the pattern 10 to be aligned when the pattern to be superimposed is shifted in the X-axis direction with respect to the design value, and Fig. 8 is the case where the pattern to be superimposed is shifted in the Y-axis direction with respect to the design value.
This is a specific example showing the correlation between b and the alignment mark 11a. As described above, it is determined whether the intervals b1 to b4 are within the allowable range with respect to the design value, and the interval bl
If ~b4 is within the allowable range with respect to the design value, the inspection is passed, and exposure and development are performed to form a resist pattern. Further, if the spacing ~b4 is outside the allowable range with respect to the design value, move the second mask to bring the overlay accuracy within the allowable range with respect to the design value, and then perform exposure and development, A resist pattern is formed.

In this second embodiment, the outer frames 2a and 6a of the alignment mark 10a and the alignment mark lla have a square shape with a part cut out (see FIGS. 4 and 5).
(see figure), outer frame 2b of alignment pattern 10b
and the outer frame 6a of the alignment mark lla do not overlap. Therefore, there is no possibility of deviation in the line width of the outer frame due to interference between these outer frames 2b and 6a. It becomes possible to do this.

Therefore, in the process of forming the resist pattern, after performing position control by mask alignment as described above, an overlay accuracy inspection is performed.This overlay accuracy inspection involves bringing the second mask into close contact with the wafer case,
This is because the wafer may move, so there is a possibility that the desired resist pattern may not be formed.

The overlay accuracy inspection will be described in detail below.

This overlay accuracy inspection is performed using the first mask and second mask used for the mask alignment.

That is, when mask alignment is performed using the first and second masks shown in the first embodiment, after exposure and development, the alignment pattern 1b and the position as shown in FIG. A matching pattern 5b is formed on the wafer. Therefore, the intervals a and -a4 are measured again, and the amount of deviation from the design value due to overlapping is inspected simultaneously in the X-axis direction and the Y-axis direction. If the amount of deviation is outside the allowable range for the design value, remove the resist from the patterned wafer using a sulfuric acid boiler, reapply the resist, and input the offset amount corresponding to the amount of deviation. After aligning the masks again, a resist pattern is formed on the wafer by exposure and development.
~Measure a4. Then, repeat this process until these intervals a1-84 are within the allowable range for the design value,
This is to determine whether the overlay accuracy is acceptable or not.

In addition, when mask alignment is performed using the first and second masks shown in the second embodiment, after exposure and development, the alignment pattern 10b and the position as shown in FIG. A matching pattern llb is formed on the wafer. In this case as well, one interval is used as described above.
By measuring ~b4, the amount of deviation from the design value due to overlapping can be inspected simultaneously in the X-axis direction and the Y-axis direction.

If the overlapping pattern deviates from the design value in the X-axis direction as shown in Figure 7, or in the Y-axis direction as shown in Figure 8,
If there is deviation in the axial direction, that is, if the spacing, ~b, is outside the allowable range for the design value, remove the resist from the patterned wafer using a sulfuric acid boiler, etc., and remove the offset corresponding to the amount of deviation. After inputting the data, resist is applied again, exposed and developed to form a resist pattern. Then, a desired resist pattern is formed by repeating this process until the distance -b falls within the allowable range for the design value. In this embodiment, since the pattern is formed using the first and second masks having the outer frames 2a and 6a in the shape of a square with a part cut out, the same steps as in the case of mask alignment are performed.
This is advantageous because there is no possibility of deviation in line width of the outer frame due to interference between the outer frames 2a and 6a.

After alignment is performed by mask alignment in this way, a desired resist pattern can be efficiently formed by inspecting the alignment accuracy based on the pattern formed by mask alignment. Moreover, since the precision of mask alignment is good, it can be expected to eliminate the need to re-form resist patterns at the inspection stage.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and may be modified without departing from the scope of the invention. For example, in overlay accuracy inspection, alignment marks are used to perform mask alignment (position After performing the overlay accuracy inspection according to the present invention, the pass/fail of the resist pattern may be determined by the overlay accuracy inspection according to the present invention, and after forming a pattern on the wafer by the reduction projection exposure method, the overlay accuracy inspection according to the present invention It is also possible to determine whether the resist pattern is acceptable or not. Furthermore, in high-resolution pattern formation, it is most rational to perform an inspection using the overlay accuracy inspection according to the present invention after exposure and development are performed using a reduction projection exposure method.

light! (2) and Consequences As detailed above, in the present invention, both the mark for alignment and the mark for alignment are parallel to an outer frame formed in a square shape and a pair of opposite sides of the outer frame. The marks are formed on the first and second masks so that the center line of the alignment target mark and the center line of the alignment mark are orthogonal to each other. By arranging the second mask in such a manner that the center line of the alignment pattern formed based on the alignment mark and the center line of the alignment mark are orthogonal to each other, The correlation between the alignment pattern and the alignment mark is approximately grid-like in plan view.

Therefore, by measuring the distance between the outer frame and the center line, it is possible to simultaneously measure the amount of deviation in the X-axis direction and the Y-axis direction. Then, by moving the second mask to bring the amount of deviation due to overlapping within an allowable range with respect to the design value, and then performing exposure and development, highly accurate mask alignment can be easily performed. Moreover, compared to the conventional vernier method, the alignment marks and alignment marks are smaller and do not need to be placed in the TEG area or scrub line (and occupy less space on the wafer).
That is, regarding the formation of a resist pattern, it is possible to further improve the efficiency compared to the conventional method.

Furthermore, this mask alignment method is not affected by changes in the thickness of the resist formed on the wafer, and is excellent in practical terms.

Furthermore, since these marks occupy a small area as described above, they can also be placed inside a chip constituting an LSI.

Furthermore, when a mark for alignment and an alignment mark in which a part of the square outer frame is missing are formed on each mask, and these masks are used, the mark for alignment and the position The correlation with the alignment mark forms a planar visual plane, and mask alignment can be easily performed by measuring the distance between the outer frame and the center line, as described above. Therefore, it goes without saying that the same effect as described above is achieved.Moreover, in this case, since the outer frame of the pattern to be aligned and the outer frame of the alignment mark do not overlap each other, these outer frames There is no "shift" in the line width of the outer frame due to mutual interference, and even more precise mask alignment can be performed.

Furthermore, the method for forming a resist pattern according to the present invention includes:
In the overlay accuracy inspection, these patterns are formed on the wafer based on the alignment marks and alignment marks of the first and second masks used for mask alignment, so the outer frame and center By measuring the distance from the line, the amount of deviation in the X-axis direction and the Y-axis direction can be determined at the same time, and it is possible to determine whether or not the inspection is successful.

In addition, when performing an overlay accuracy inspection using an alignment mark with a part of the square outer frame missing and the first and second masks on which the alignment mark is formed, As in the case of mask alignment described above, the correlation between the pattern to be aligned and the pattern for alignment is on a plane view. Even in this case, by measuring the distance between the outer frame and the center line, the amount of deviation in the X-axis direction and the Y-axis direction can be determined at the same time, and it is possible to determine whether or not the inspection is successful.

In other words, even when mask alignment is performed using alignment marks or a reduction projection exposure method, by applying the above-mentioned overlay accuracy inspection method, extremely high-precision inspection can be performed efficiently. .

As described above, according to the method for forming a resist pattern according to the present invention, a desired resist pattern that matches the device design can be easily formed, and a semiconductor element with even higher quality can be manufactured.

In addition, it is possible to shorten the inspection time, etc., so it is possible to shorten the overall time of the photolithography process and the semiconductor device manufacturing process, which has the remarkable effect of improving the productivity of semiconductor devices. There is.

[Brief explanation of drawings]

FIG. 1 is a plan view showing an example of the correlation between the alignment mark (alignment pattern) and the alignment mark (alignment pattern) used in the resist pattern forming method according to the present invention. , FIG. 2 is a plan view of the alignment mark in FIG. 1, FIG. 3 is a plan view of the alignment mark in FIG. 1, and FIG. 4 shows a second embodiment of the alignment mark. FIG. 5 is a plan view showing the second embodiment of the alignment mark, and FIG. 6 is the alignment mark (alignment pattern) and alignment mark in the second embodiment. FIG. 7 is a plan view showing the correlation between the positioning mark (positioning pattern) and the positioning pattern when the positioning mark (positioning pattern) is misaligned in the X-axis direction in the second embodiment. A plan view showing the correlation with the alignment mark (alignment pattern), FIG. 8 is a plan view showing the correlation with the alignment mark (alignment pattern) in the second embodiment.
A plan view showing the correlation between the pattern to be aligned and the alignment mark (alignment pattern) when the pattern is shifted in the Y-axis direction, and Figure 9 is for explaining the principle of the conventional vernier method. This is a diagram. la, loa... mark for alignment, lb. fob: pattern for alignment, 2a, 2b. 6a, 6b... Outer frame, 3a, 7 a-... Side, 4a. 4b, 8a, 8b-center line, 5a, 1l
a-... Alignment mark, 5b, llb... Alignment pattern.

Claims (4)

[Claims] (1) A resist pattern in which a pattern is repeatedly formed on a wafer while performing mask alignment using a first mask on which alignment marks are formed and a second mask on which alignment marks are formed. In the forming method, the mark for alignment and the mark for alignment are both formed from an outer frame formed in a square shape and a center line parallel to a pair of opposing sides of the outer frame. and the respective marks are formed on the first and second masks so that the center line of the alignment target mark and the center line of the alignment mark are orthogonal to each other, After forming a pattern on a wafer using a mask, applying a resist on the pattern, and then using the second mask to form a pattern based on the alignment mark of the first mask. A method for forming a resist pattern, comprising forming a resist pattern while performing alignment with a pattern to be aligned. (2) Forming marks for alignment and alignment marks in which a part of the square outer frame is missing on first and second masks, and using these first and second masks. 2. The method of forming a resist pattern according to claim 1, further comprising performing positioning. (3) A resist pattern forming method in which a resist pattern is formed while inspecting the overlay accuracy of the resist patterns using the first and second masks according to claim (1), comprising: After forming a pattern on the wafer using a mask, a resist is applied on the pattern, and then a pattern is formed on the resist using the second mask, and then a pattern is formed on the resist using the first mask. The alignment accuracy of the alignment pattern formed based on the alignment mark of the second mask and the alignment pattern formed based on the alignment mark of the second mask is inspected to determine the alignment accuracy of the resist pattern. A resist pattern forming method characterized by determining pass/fail. (4) The method for forming a resist pattern according to claim (3), wherein the first and second masks according to claim (2) are used to determine whether or not the resist pattern is acceptable.