JPH0384893U - - Google Patents

Info

Publication number
JPH0384893U
JPH0384893U JP14409689U JP14409689U JPH0384893U JP H0384893 U JPH0384893 U JP H0384893U JP 14409689 U JP14409689 U JP 14409689U JP 14409689 U JP14409689 U JP 14409689U JP H0384893 U JPH0384893 U JP H0384893U
Authority
JP
Japan
Prior art keywords
signal
test
circuit
generation circuit
signal generation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14409689U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14409689U priority Critical patent/JPH0384893U/ja
Publication of JPH0384893U publication Critical patent/JPH0384893U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案に係る画像表示装置のセルフテ
スト回路の一実施例を示すブロツク回路図、第2
図は一般的なパソコンの構成を示す概略図である
。 1……パソコン本体、3……画像表示装置(C
RTデイスプレイ装置)、7……映像信号ライン
、9……切換え回路、11……同期信号ライン、
15……同期信号検出回路、17……テスト信号
発生回路、19……プリアンプ、21……同期信
号処理回路、P1,P2,T1,T2……固定端
子、P3,T3……可動端子、Tr……トランジ
スタ。
FIG. 1 is a block circuit diagram showing one embodiment of a self-test circuit for an image display device according to the present invention, and FIG.
The figure is a schematic diagram showing the configuration of a general personal computer. 1...PC body, 3...Image display device (C
RT display device), 7...Video signal line, 9...Switching circuit, 11...Synchronization signal line,
15...Synchronization signal detection circuit, 17...Test signal generation circuit, 19...Preamplifier, 21...Synchronization signal processing circuit, P1 , P2 , T1 , T2 ...Fixed terminal, P3 , T3 ...Movable terminal, Tr...Transistor.

Claims (1)

【実用新案登録請求の範囲】 (1) 映像信号および同期信号の伝送される信号
ラインと、 テスト用の映像信号および同期信号を作成出力
するテスト信号発生回路と、 前記信号ラインに挿入され前記信号ラインを伝
送した信号と前記テスト用信号発生回路からの出
力信号を切換え出力する信号切換え回路と、 前記信号ラインを伝送する同期信号の無信号状
態を検出して前記テスト信号発生回路を起動させ
るとともに、前記テスト用信号発生回路からの出
力信号を選択するよう前記信号切換え回路を動作
させる無信号判別回路と、 を具備してなることを特徴とする画像表示装置の
セルフテスト回路。 (2) 前記無信号判別回路は前記テスト信号発生
回路への電源レベルを制御してこれを起動制御す
るとともに、前記信号切換え回路は前記テスト信
号発生回路への電源レベル状態によつて切換え制
御される請求項1記載の画像表示装置のセルフテ
スト回路。
[Claims for Utility Model Registration] (1) A signal line through which a video signal and a synchronization signal are transmitted; a test signal generation circuit that generates and outputs a test video signal and a synchronization signal; and a test signal generation circuit inserted into the signal line to transmit the signal. a signal switching circuit that switches and outputs the signal transmitted through the line and the output signal from the test signal generation circuit; detecting a no-signal state of the synchronization signal transmitted through the signal line and activating the test signal generation circuit; A self-test circuit for an image display device, comprising: a no-signal discrimination circuit that operates the signal switching circuit to select an output signal from the test signal generation circuit. (2) The no-signal discrimination circuit controls the power level to the test signal generation circuit to control its activation, and the signal switching circuit is switched and controlled depending on the state of the power level to the test signal generation circuit. A self-test circuit for an image display device according to claim 1.
JP14409689U 1989-12-15 1989-12-15 Pending JPH0384893U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14409689U JPH0384893U (en) 1989-12-15 1989-12-15

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14409689U JPH0384893U (en) 1989-12-15 1989-12-15

Publications (1)

Publication Number Publication Date
JPH0384893U true JPH0384893U (en) 1991-08-28

Family

ID=31690832

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14409689U Pending JPH0384893U (en) 1989-12-15 1989-12-15

Country Status (1)

Country Link
JP (1) JPH0384893U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008118453A (en) * 2006-11-06 2008-05-22 Sanyo Electric Co Ltd Video display
JP2022051164A (en) * 2020-09-18 2022-03-31 カシオ計算機株式会社 Projection device, light emission control method, and program

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008118453A (en) * 2006-11-06 2008-05-22 Sanyo Electric Co Ltd Video display
JP2022051164A (en) * 2020-09-18 2022-03-31 カシオ計算機株式会社 Projection device, light emission control method, and program

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