JPH0384927A - Manufacture of semiconductor device provided with multilayer interconnection - Google Patents

Abstract

PURPOSE:To flatten the surface of a semiconductor substrate, to enhance a flatness of an interlayer insulating film and to prevent a defective connection of an interconnection by a method wherein a polyimide film containing silicon is formed, by a coating operation, as the interlayer insulating film on a semiconductor substrate. CONSTITUTION:An SION film 4 is etched and removed isotropically by making use of a resist film 5 as a mask; opening parts 11a, 11b are formed in the SION film 4 on aluminum interconnections 3a, 3b. The resist film 5 is removed by using a plasma or the like; after that, a polyimide film 6 containing silicon is applied to the whole surface of a substrate by a coating operation and is baked. Corners at opening parts 10a, 10b of a resist film 7 are rounded by a heat treatment. An etching-back operation is executed in an etching rate ratio of the resist film 7 to the polyimide film 6 containing Si at about 1 to 1; the polyimide film 6 containing Si inside the opening parts 11a, 11b is removed to form through holes 8a, 8b. Aluminum interconnections 12a, 12b which are connected to the aluminum interconnections 3a, 3b via the through holes 8a, 8b are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device having multilayer wiring in which a glabellar insulating film and through holes are provided between the wirings.

[Prior Art] In recent years, in order to achieve higher density and higher performance in vLSIs, wiring has been multilayered, and VLSIs with three- or four-layer wiring structures have been commercialized. In particular, since bipolar VLSI is used in the heart of computers and the like, it is required to have high reliability and requires advanced manufacturing technology.

In such VLSIs, it is required to form interlayer films with excellent electrical insulation and water resistance, but an analysis of previous defective products shows that most of the defects were caused by the metallization system, especially in the stepped areas. There are many defects caused by the shape of the wiring covering. These defects are mainly caused by problems in the coverage of the upper layer wiring between the ends of the lower layer wiring and between the wirings, and the coverage of the upper layer wiring in the through-hole portion.

FIGS. 3(a) and 3(b) are cross-sectional views showing an example of a conventional method for manufacturing a semiconductor device having multilayer wiring.

In FIG. 3(a), an SOG film (Spin On Glass film; coated and baked film) is formed as a so-called step sloping in order to improve the coverage of the upper layer wiring between the ends of the lower layer wiring and between the wirings. And this SOG film is -
Inside the shell, PCVD method (Plasma Chemical
It is used in combination with an inorganic insulating film deposited using a vapor deposition method.

As shown in FIG. 3(a), first, a 5i02 film 32 is deposited on a silicon substrate 31 on which elements are formed. next%
S t 02 [After depositing an aluminum film on 32, selective patterning is performed to form an aluminum wiring 33
form at 33 b* 33 c. Next, a 5ION film (Si-0
After depositing the -N-based insulating film 34, an SOG film 36 is deposited by a coating and baking method, and then a 5ION film 36 is deposited. After that, aluminum wiring 3 is placed on this 5ION film 38.
7a.

37b is selectively formed.

In the conventional method of such a process, the film thickness of the lower layer aluminum wiring 33at 33b+33c is 1.0 μm.
In the case of m, the film length of the SON film 34 and the SOG film 3 is 5ION
The film thickness of the interlayer insulating film composed of the film 36 is approximately 1.0μ.
m, the surface of this interlayer insulating film is flattened, and the lower layer aluminum wiring 33a* 33bs 33c
Upper layer aluminum wiring 37 between the ends and wiring
The coverage of a and 37b has been improved.

Furthermore, in FIG. 3(b), the coverage of the upper layer wiring in the through-hole portion is improved.

As shown in FIG. 3(b), after selectively forming an aluminum wiring 33d on the SiO2 film 32, a 5 ION film 34 and an SOG film 38 with a length of 55 ION are sequentially formed. Next, after a resist film 38 is deposited on the entire surface of the substrate, the resist film 38 directly above the aluminum wiring 33d is selectively removed.

Next, using this resist film 38 as a mask, about 100 pa
5 using a mixed gas CCFa +02) plasma of
Isotropic openings 39 are formed by etching and removing the ION film 36 in the same direction. Furthermore, using the resist film 38 as a mask, the SOG film 3 was etched to a film length of 55 ION by anisotropic etching using CF4 gas plasma of approximately 10 pa.
Anisotropic openings 40 are formed by selectively removing membrane 36.
form. As a result, the through-hole portion (isotropic opening portion 39 + anisotropic opening portion 40) is formed in a two-stage shape, and the coverage of the upper layer wiring in the through-hole portion is improved.

[Problems to be Solved by the Invention] However, the above-described conventional method for manufacturing a semiconductor device having multilayer wiring has the following problems. That is, in conventional semiconductor devices, in devices that require high speed performance, the parasitic capacitance of wiring mainly controls the functional speed, so by increasing the thickness of the interlayer insulating film, the capacitance C of the interlayer insulating film can be reduced This reduces the parasitic capacitance of the wiring. However, if the interlayer &tg (SION film 34, 38) is formed thickly, there is a problem that when a through hole is formed, a connection failure occurs in the wiring due to its shape. This problem will be explained based on FIG. 4.

FIGS. 4(a) and 4(b) are cross-sectional views showing examples of wiring defects in the conventional manufacturing method of a semiconductor device having multilayer wiring. In FIGS. 4(a) and 4(b), the same parts as those in FIG. 3(b) are given the same reference numerals, and detailed explanation thereof will be omitted.

As shown in FIG. 4(a), the 5ION films 34a and 5I
The ON film 36a is the conventional 5ION film 34 and the 5ION film 3.
The film thickness is twice that of 6. Therefore, when the aluminum wiring 37c is deposited on this board,
Since the step of the anisotropic opening 40 is doubled, the step coverage of the aluminum wiring 37c deteriorates and the constriction 41
is formed. On the other hand, in the isotropic opening 39, the 5ION film 38a above it has an extremely steep shape, so that a constriction 42 also occurs. This poses a problem in that the connection resistance of the wiring increases significantly and the electromigration resistance decreases significantly.

Furthermore, if gold (Au) wiring, which has better electromigration resistance and stress migration resistance than aluminum, is formed as the upper layer wiring instead of the aluminum wiring 37c, this problem becomes even more pronounced.

Usually, a lift-off method or an electric field plating method is used to form Au wiring. For this reason, as shown in FIG. 4(b), titanium (Ti) [4
3 is deposited by sputtering to prevent the occurrence of purple blobs due to contact between Al and Au. Next, T
Platinum (Pt) on the i film 43! 1a44 is formed by sputter deposition.

Thereafter, Au is deposited using the Ti film 43 and the PT film 44 as plating electrodes.

In addition, in order to easily lift off the Au film, for example, the thickness of the Ti film 43 is set to about 4000λ, and the thickness of the Ti film 43 is set to about 4000λ,
It is necessary that the film thickness of 44 be about 2000λ, and the sum of both film thicknesses should be about 6000 Å or less.

However, even in this case, the coverage of 'rtg4s is reduced due to the shapes of the isotropic openings 39 and the anisotropic openings 40, and the TiWX 43 becomes locally overhanging. For this reason, the PT film 44 is not adhered to the upper part of the slope of the isotropic opening 39 and the side wall of the anisotropic opening 40, resulting in disconnection. Therefore, since it is not possible to form a predetermined Au wiring, the connection resistance increases significantly.

Furthermore, this tendency also applies to the plating electrode (Ti film 43 + Pt film 44).
) appears more prominently as it is formed thinner.

Furthermore, inorganic compound-based S formed by coating and firing method
The OG film has the property that cracks are more likely to occur when it is applied thickly. For this reason, there is also the problem that sufficient flatness cannot be ensured at the ends of the wiring and between the wirings.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a method for manufacturing a semiconductor device having multilayer wiring, which has excellent flatness of an interlayer insulating film and can prevent poor connection of wiring.

[Means for Solving the Problems] A method for manufacturing a semiconductor device having multilayer wiring according to the present invention includes a step of forming a first wiring layer on a semiconductor substrate, and a step of forming a semiconductor substrate including the first wiring layer. d) an insulating film in which openings are selectively formed on the first wiring layer by isotropic etching, a silicon-containing polyimide film formed by coating on top of the insulating film, and a silicon-containing polyimide film on top of the first wiring layer; a step of forming a resist film selectively except for the area directly above the wiring layer; a step of rounding the corners of the resist film by heat treatment; and a step of forming the resist group and the polyimide film into
etching at an etching rate ratio of 1 to 1 to remove the polyimide film in the opening; and forming a second wiring layer connected to the first wiring layer on the substrate. It is characterized by

[Function] In the present invention, the surface of the semiconductor substrate is flattened by forming a silicon-containing polyimide film on the semiconductor substrate as an interlayer insulating film by coating. This silicon-containing polyimide film has electrical insulation and water resistance equivalent to that of an inorganic insulating film formed by the PCVD method, as well as superior crack resistance. It is possible to form a coating film several times to several tens of times larger. Therefore, the surface of the semiconductor can be planarized with extremely high accuracy, and the interlayer capacitance of a semiconductor device having multilayer wiring can be reduced.

Further, after forming an opening in the insulating film on the first wiring layer by isotropic etching, selectively removing the resist film immediately above the opening, and rounding the corners of this resist film by heat treatment, This resist film and polyimide film are etched at an etching rate ratio of 1:1 to expose the first wiring layer.

Therefore, the shape of the resist film with rounded corners is reflected in the shape of the polyimide film after etching, and the shape of the polyimide film and the shape of the opening are smoothly connected. A through hole can be formed with a smooth shape. Therefore, by forming a second wiring layer connected to the first wiring layer through this through hole in the next step, it is possible to prevent connection failures from occurring.

[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.

FIGS. 1(a) to 1(d) are cross-sectional views showing, in order of steps, a method for manufacturing a semiconductor device having multilayer wiring according to a first embodiment of the present invention.

First, as shown in FIG. 1(a), SiO2i2 is deposited on a silicon substrate 1 on which elements are formed.

Next, after depositing an aluminum film on the S102 film 2, a selective pattern is formed to form an aluminum wiring 3a.
Form t 3bt 3c. Next, 5ION with a thickness of about 5000λ, for example, is deposited on the entire surface of this substrate by the PCVD method.
After depositing the film 4, a resist film 5 is formed on the SIONM4. Next, the resist film 5 directly above the aluminum wirings 3a and ab is selectively removed to form the openings 9a+9.
After forming 5IONII!b, using this resist film 5 as a mask, a mixed gas (CF4+Oa) plasma of, for example, about 100pa is used. Openings 11a and 11b are formed in the 5ION film 4 on the aluminum wirings 3a and 3b by etching away the 5ION film 4 in the same direction. The openings 11a, flb have a bowl shape with the open side facing upward, and are formed with a large slope downward. This slope is formed by overetching, but if extreme overetching is performed, the slope will gradually become smaller, so it is necessary to stop the etching with a slight overetching. For example, with 10% overetching, the inclination angle of the 5ION film 4 with respect to the surface of the aluminum wiring 3as3b below the openings 11a and llb is approximately 3
It becomes 0 degrees.

Next, as shown in FIG. 1(b), the resist film 5 is
After removal with plasma or the like, the entire surface of this substrate is coated with a film thickness of approximately eoo at the openings 11a and 11b, for example.
A polyimide film 6 containing silicon (hereinafter referred to as Si-containing polyimide film) 6 is deposited and further betaened. As this Si-containing polyimide film 6, for example, an organic film having the following structure may be used. This film has better heat resistance, adhesiveness, insulation, etc. than ordinary polyimide films.

However, Rt to R4 are aromatic molecules.

Next, the NSISi-containing polyimide film 6, openings 11a, l
After forming a resist film 7 having a thickness of about 2000 to 5000λ thicker than the thickness of the Si-containing polyimide film 8 in lb, a resist film 7 is formed in the resist M7 in the area directly above the aluminum arrangement TiA 3 a +3b compared to the openings 11a and 11b. Thus, openings 10a+10b having a larger opening diameter of about 5000 Å are formed. Next, the opening 10 of the resist film 7 is formed by heat treatment.
The corners in a and 10 b are rounded and shaped as shown by the broken line. The shape of this resist 1iE7 can be freely changed depending on heat treatment conditions such as temperature and heating time and the type of resist used. For example, as a resist, 0FPR800-50 (trade name; manufactured by Tokyo Applied Chemical Co., Ltd.)
When N2 baking is performed at a heating temperature of 150° C. for about 30 minutes, the inclination angle of the resist film 7 at the openings 10a and 10b reaches about 50 to 60 degrees.

Next: As shown in FIG. 211 (C), the etching rate ratio between the resist film 7 and the Si-containing polyimide film 6 is approximately 1.
The entire surface of this substrate is etched back by the RIE method under the conditions that 5IONIIK4 is not etched, and the Si-containing polyimide B in the openings 11a and flb is etched back.
6 is removed to form through holes 8a and 8b. To meet this condition, for example, 02 gas plasma of about 5 pa may be used. As a result, the shape of the resist film 7 with rounded corners is reflected in the shapes of the through holes 8a, 8b, so that the through holes 8a, 8b have smooth shapes. Note that if the SION film 4 is etched in this etching process, the shape of the through hole 8as8b will be extremely poor, and in extreme cases it will become an overhanging shape, so it is necessary to appropriately select the etching conditions.

Next, as shown in FIG. 1(d), after removing the resist film 7 remaining on the S1-containing polyimide film 6, an aluminum film is deposited on the entire surface of the substrate and further selectively removed. Aluminum wiring 12a connected to aluminum wiring 3a, 3b via hole 8at8b
, 12b. Thereby, a semiconductor device having multilayer wiring can be manufactured.

According to this example, the relative dielectric constant of S1-containing polyimide I [I8 is 3, which is 1/2 of the relative dielectric constant (6) of the conventional 5ION film, so the capacitance of the interlayer insulating film can be greatly increased. can be reduced to Further, since it is easy to increase the film thickness of Si-containing polyimide lI6, it is easy to further reduce the capacitance.

Further, according to this embodiment, the through holes 8a s8b
Since it is smooth, excellent coverage can be obtained. For example, the thickness of the 5ION film 4 is 5000 Å, the thickness of the Si-containing polyimide film 6 in the openings 11a and 11b is 1.0 μm, and the openings 11a and 1 of the 5ION film 4 are
When the opening diameter at the upper end of 1b is 1.5 μm and the aluminum wiring 12 at 12 b is deposited by sputtering, the coverage is about 70%, and sufficient coverage can be ensured.

FIGS. 2(a) to 2(C) are cross-sectional views showing, in order of steps, a method for manufacturing a semiconductor device having multilayer wiring according to a second embodiment of the present invention. This embodiment differs from the first embodiment in that the photoresist process is performed once, so the same components as in FIG. 1 are given the same reference numerals and detailed explanation thereof will be omitted.

First, as shown in FIG. 2(a), after forming a 5iOz film 2 on a silicon substrate 1, an aluminum wiring 3a* is formed.
Form 3bs 3c. Next, S l0NIf having a film thickness of about 3000λ, for example, is deposited on this substrate by the PCVD method.
After depositing X4, aluminum wirings 3a and 3b are formed on 5IONj15E4 by coating.

A Si-containing polyimide film 6 having a film thickness of about 4000λ, for example, is formed on 3c. Furthermore, resist on Si-containing polyimide IIB! % 13, openings 14a and 14b are selectively formed in the resist film 13 directly above the aluminum wirings 3a and 3b. At this time, opening 1
4a and 14b are formed so that their sides are as vertical as possible.

Next, as shown in FIG. 2(b), the St-containing polyimide WX6 and the resist film 13 are simultaneously etched under the same conditions as in the first embodiment, and the Si in the openings 14at14b is etched.
While removing the polyimide M6 contained therein, the resist film 13 is removed.
decrease the film thickness.

After that, this Si-containing polyimide g6 and resist) 11
Using 13 as a mask, the 5ION film 4 is removed by etching in the same direction. Then, the openings 14a and 14b are formed by heat treatment.
The corners of the resist film 13 are rounded to form resist WX13.
Make it into the shape shown by the dashed line.

Next, as shown in FIG. 2C, the 81-containing polyimide film 6 and the resist film 13 are removed by etching at the same time using 02 plasma under the same conditions as in the first embodiment, thereby forming a layer on the aluminum wiring 3a+3b. Through hole 8
Form a+8b.

Then, after removing the remaining resist film 13, by forming upper layer wiring at a predetermined position, a semiconductor device having multilayer wiring can be manufactured.

This embodiment is effective when the film thickness of the S1-containing polyimide film 8 is relatively thin at 5001)λ on the aluminum wirings 3a and 3b, and the film thickness of 5IONfi4 is as thin as 3000λ. Therefore, it is ideal for application to devices that require a relatively small ground level difference and small through-hole dimensions.

[Effects of the Invention] As explained above, according to the present invention, the crack resistance is superior to that of the conventional SOG film, the coating film can be easily formed thickly, and the silicon-containing film has a low dielectric constant. The surface of the semiconductor substrate is flattened by applying a polyimide film. Therefore, the surface of the semiconductor can be planarized with extremely high accuracy, and the interlayer capacitance of a semiconductor device having multilayer wiring can be reduced.

In addition, an opening is formed in the insulating film on the top of the first wiring layer by isotropic etching, and the resist film with rounded corners and this polyimide film are etched simultaneously at the same etching rate to form an external shape of the polyimide film. Since the outer shape of the opening is connected to the outer shape of the opening, a smooth-shaped through hole can be formed.

Therefore, it is possible to prevent wiring connection failures, and to manufacture a semiconductor device having multilayer wiring that is high-speed and highly reliable.

[Brief explanation of drawings]

FIGS. 1(a) to (d) are cross-sectional views showing the manufacturing method of a semiconductor device having multilayer wiring according to the first embodiment of the present invention in order of steps, and FIGS. 3(a) and 3(b) are cross-sectional views illustrating a method for manufacturing a semiconductor device having multilayer wiring according to the second embodiment in order of steps, and FIGS. 3(a) and 3(b) show an example of a conventional method for manufacturing a semiconductor device having multilayer wiring. 4(a) and 4(b-) are cross-sectional views showing examples of wiring defects in the conventional manufacturing method of a semiconductor device having multilayer wiring. 1.31; Silicon substrate, 2,32; 5i02 film, 3a
,sb,3c+ 12aw 12b+ 33a*3
3b, 33c, 33d, 37a, 37b, 37C; Aluminum wiring, L 34, 34a* 38° 38a; 5
IONB, 5t L 13t 38; resist film, e
ast-containing polyimide membrane, 8 al 8 b; through-hole k, 9a+ 9b+ 10a, iob. 11a+ 11b, 14ay 14b; opening, 3
5; SOG film, 39; isotropic opening, 40; anisotropic opening, 41, 42; < fin N 43 ; T film, 44
;Pt film

Claims (1)

[Claims] (1) forming a first wiring layer on the semiconductor substrate;
An insulating film in which openings are selectively formed on the first wiring layer by isotropic etching on the entire surface of the semiconductor substrate including the first wiring layer, and silicon formed by coating on the insulating film is formed. the polyimide film and the first film on top of it.
a step of forming a resist film selectively except for the area immediately above the wiring layer; a step of rounding the corners of the resist film by heat treatment; and a step of etching the resist film and the polyimide film at a one-to-one etching rate. a step of removing the polyimide film in the opening by etching the polyimide film in the opening; and a step of forming a second wiring layer connected to the first wiring layer on the substrate. A method for manufacturing a semiconductor device having wiring.