JPH0385604A - Method and device for determining arithmetic operation order for ladder diagram input part - Google Patents

Abstract

PURPOSE:To omit unnecessary arithmetic operation, and to execute circuit operation at high speed by converting a ladder diagram into a directed graph, and executing preferentially the arithmetic operation from the path of the shortest arithmetic operation execution time. CONSTITUTION:A vertical connection line at a ladder diagram input part is grasped as a point (apex), and the connection line in a horizontal direction is grasped as a directed side, and the directed graph is formed in all. A logical value '1' is set while only the apex 0 is kept in ON-state, and the logical value '0' is set while the apexes 1, 2 other than the apex 0 are kept in OFF-state, and the arithmetic operation between two apexes is executed. Then, at the point of time when it becomes clear that the path (A) transmitted the logical value '1', the arithmetic operation at other paths (B), (C) is omitted, and output processing is executed. Thus, since the arithmetic operation is executed preferentially from the path of the shortest time required for logical operation, the processing time of a sequence program is speeded up as a whole executed object.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention provides a ladder diagram input unit that determines an optimal processing order to speed up calculations in a sequence control device that can be programmed using a ladder diagram. The present invention relates to a method for determining the order of operations and an apparatus therefor.

(Prior Art) Conventionally, control methods for an arithmetic unit in a sequence controller that can be programmed using a ladder diagram can be broadly classified into the following two control methods. First, the first control method is to input the pool algebraic expression by "LOAD", "AND"
This method uses mnemonic commands such as ``, ``OR'', and ``5TORE'' to control the execution operations using the Borland technique.A second control method is disclosed in Japanese Patent Laid-Open No. 1987-705. In this method, a ladder diagram is made to correspond to a switch matrix, and the logical value in the last column of the ladder diagram input section is obtained by column cyclic calculation.

(Problem to be Solved by the Invention) However, in the control method using the conventional Borland technique described above, in order to obtain the calculation result, a series of two steps starting from "LOAD" and ending with '5TORE'° are required.
All monic operations had to be performed. In other words, FIG. 11 is an example in which the ladder diagram shown in FIG. 5 corresponds to a command group using the Borland technique. If the state of d can be checked and the result can be output immediately, other unnecessary operations can be omitted.

However, in the control method using the Borland technique,
No consideration was given to increasing the execution speed by omitting such operations.

On the other hand, in the control method using column cyclic operations,
In order to obtain calculation results, the ladder diagram is made to correspond to a switch matrix in which each row and column of contact information and one branch information can be specified, and calculations related to contact information and calculations related to branch information are alternately performed in each row and column. I had to carry out the following steps. That is, even in this method, the output result could be obtained only after all calculations were completed. For example, FIG. 12 is an example in which the ladder diagram in FIG. 5 is made to correspond to a switch matrix. here,
Switches placed on vertical connection lines correspond to branch information, and switches placed on horizontal connection lines correspond to connection information.

As mentioned above, the control method using the Borland technique and the column cyclic? In any of the control methods using rii's, the time required for calculation is mainly determined by the control form (hardware), and as long as the same control form (hardware) is used, it is difficult to further speed up the calculation. There was a problem.

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a ladder diagram input unit capable of determining the IA processing order so that calculation results can be obtained at the fastest speed and output processing can be performed. An object of the present invention is to provide a method and device for determining the order of operations.

(Means for Solving the Problems) The present invention provides a method for determining the operation order of a ladder diagram input unit in a sequence control device that can be programmed using a ladder diagram, in which an optimal processing order is determined in order to speed up the calculations. The above-mentioned object of the present invention is to turn on/off the intersection of the vertical connection line of a ladder diagram representing program contents and the boundary line of the input section and output section with the horizontal connection line of the ladder diagram. At the top with information,
The on/off information is transmitted only from left to right on the horizontal connection line, and the a contact and the b contact on the horizontal connection line are placed on the directed side of the on/off information. The ladder diagram is converted into a directed graph by corresponding to the gates that control the transmission of information, and information is transmitted between the vertices corresponding to the bus line, which is the leftmost vertical connection, and the vertices corresponding to the boundary line. All possible paths are extracted and weighted according to the complexity of the process, and the initial state is set to the on state for the vertices corresponding to the generatrix, and the off state for the other vertices. Then, when the gate is in a conductive state, the process of transmitting the information of the corresponding outflow side vertex to the inflow side vertex is repeated for all the gates in one passage to complete the transmission of the passage. This is achieved by determining whether the vertex corresponding to the boundary line between the input section and the output section is in the on state by performing the process of determining the state in order from the path with the least weight. Further, a storage means in which the execution object is stored, a vertex logical value storage means in which the logical values of the sending and receiving vertices are stored, and a contact logical value storage means in which the logical values of the contacts on the directed edges are stored, A logical operation is performed based on the logical value of the transmitting vertex stored in the vertex logical value storage means and the logical value of the corresponding contact point on the directed edge stored in the contact logical value storage means to determine the value of the receiving vertex. This is achieved by providing inter-vertex calculation means for calculating logical values and control means for controlling the entire calculation.

(Operation) The present invention converts a ladder diagram into a directed graph, and starts from the path with the shortest calculation execution time among the paths from the turned-on vertex of the directed graph to the vertex connected to the ladder diagram output part. By performing calculations preferentially, unnecessary calculations can be omitted, so circuit calculations can be performed faster.

(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings.

First, the operation of making a ladder diagram correspond to a directed graph will be explained using a specific example. Here, a graph is a general term for a figure that is composed of a plurality of distinguishable points or vertices and edges connecting them, and a directed graph is a graph that has edges that have directionality.

FIG. 5 is an example of a ladder diagram. In this ladder diagram, vertical connection lines are numbered O2■, ■ from the left. For convenience, the point where the boundary between the ladder diagram input section and the ladder diagram output section intersects with the horizontal connection line of the ladder diagram is assumed to be a vertex, and is called the vertex connected to the ladder diagram output section. In the ladder diagram shown in the same figure, the vertical connection lines numbered ■ also serve as vertices connected to the ladder diagram output section. Here, the ladder diagram input section is a section that connects contact information using horizontal and vertical connection lines to perform logical operations, and the contact information includes a
Regarding the logical values of the contacts and the b contacts, it is also conceivable to directly incorporate those whose results are expressed as logical values in arithmetic operations etc. instead of the a and b contacts. Further, the ladder diagram output section is a section that outputs a logical value and executes a timer, a counter, or other application instructions based on the calculation result of the ladder diagram input section.

In the example of FIG. 5, the horizontal connection by the combination of the a contact, the b contact, and the horizontal connection line is limited to the connection from the left vertical connection line to the right vertical connection line. Therefore, rather than thinking of vertical connecting lines as line segments, it is better to think of them as points in a more wood-like way.

Based on the above-mentioned purpose, the vertical connection line that enters the ladder diagram input section in Figure 5 is reconsidered as a point (vertex) in Figure 6.
It is a diagram. Here, the horizontal connection line is a curved line. By the way, if we consider this horizontal connection line as a directed edge, the whole will form a directed graph, but as it is, the correspondence with the ladder diagram is insufficient, so we will use the following two methods.
Add requirements (8) and (B).

(8) The vertices of the graph can be in an on or off state, with an on state having a logical value of "1" and an off state having a logical value of "0".

(B) The a-contact and the b-contact are placed on directed edges connecting vertices and function as gates that control the flow of information.

By adding the above two requirements (8) and (B), the ladder diagram input section of FIG. 5 has a one-to-one correspondence with the directed graph of FIG. 6 in terms of its functions.

In the ladder diagram transferred to the directed graph shown in FIG. 6 as described above, first, an area for temporarily storing the on or off state of the vertex (vertex logical value-time storage unit 2 in FIG. 2, which will be described later) is created. ), and set the logical value ``11'' to indicate that only the vertex corresponding to the bus line is on, and set the logical value ``0°'' to indicate that the other vertices are in the off state.
Set. After such settings, the calculation between the two vertices is repeated in the order of (()Q-Y or (B)〆O+■-@ or (C)■-4→■-Y in Fig. 7. As a result, if the logical value "1" at the vertex O is transmitted to the vertex ■, the vertex ■ becomes the logical value °°1°', and if the logical value "1" is not transmitted to the vertex ■, the vertex ■ becomes the logical value "o" ”, so it is outputted in the ladder diagram output unit as the calculation result of the ladder diagram input unit.

FIG. 7 shows the paths (A) (0), (
It is divided into three ways (c) and described separately. Here, a path is a path that can be followed from one vertex to another through an edge or a vertex on a graph, and if two vertices are connected by multiple edges, Each section is distinguished as a separate passage. for example,
In FIG. 7, two directed edges φ between vertices o−〇 are distinguished as (o) (D−U, (A) Q−′−@).

By the way, there are three paths (a) in Fig. 7.

If the logical value of the vertex ■ is output after calculating all of (b) and (c), the IA processing speed of the execution object will decrease, so for example, only the path (a) has a logical value °゛1°′
If the other paths (0) and (c) transmit the logical value "O°', the path (a) is the logical value" t
” as soon as it is determined that the
The calculations in (b) and (c) are omitted and output processing is performed quickly. In other words, the processing speed of the execution object is improved by performing output processing immediately when it is determined that one of the paths ((), (b), and (c) has transmitted the logical value "1". .

At that time, among the multiple paths from the vertex corresponding to the bus line to the vertex connected to the ladder diagram output section, the logical values are sequentially selected starting from the path that requires the shortest time to calculate the transmission of the logical value. We take a method that calculates the transmission of . In other words, when considered statistically, the probability of transmitting the logical value "1" and the probability of transmitting the logical value "o" can be considered to be constant in all paths, so the shortest time required for the calculation is By calculating the transmission of logical values in order, the processing speed of the execution object is further improved.

FIG. 8 shows the passage ((), IO) in FIG. 7.

When each of (C) transmits a logical value, the following (■) to (■) are each multiplied by l/2 as weighting when executing the old arithmetic operations (A) and (B).

The sum of the weights required for the calculation of each path in (c) is calculated.

(1) Operation to read the 0N10FF state of the vertex on the side flowing to the directed side (I+) The logical value of the a contact or b contact placed on the directed side and the logical value of the directed side to the left of the contact Operation (m) that takes the logical sum and sets it as the logical value of the directed edge on the right side of the contact point. Vertex of the example where the logical value at the time when the logical value operation (I+) on the directed edge is completed is input from the directed edge Here, the weight is a convenient parameter attached to select the path that can perform the logical value transmission in the shortest execution time from among multiple paths, and 1), (o), and (m), take numerical values proportional to their respective execution times.

A means for determining the order of operations between vertices using the concept of weights (tf) for operations as described above will be described below.

Figure 1 is a flowchart for determining the order of operations between vertices. By assuming conductive/non-conductive states for all directed edges on the directed graph corresponding to the ladder diagram, we can The state is simulated, and the order of operations is determined so that the path with the least weight among the possible paths in a certain state is always selected.

That is, first, as an initial setting, all vertices on the directed graph are turned off (step S1), only vertex O, which is the vertex corresponding to the generatrix on the ladder diagram, is turned on (step S2), and the subroutine '5UBI' is called ( Step S3).

In the subroutine "5UBI", first, unnecessary vertices and unnecessary directed edges are deleted (step 54). Here, an unnecessary vertex is, for example, a vertex on the side into which a directed edge flowing out from a certain vertex [phase] flows. In such a case, it is meaningless to investigate the path through the directed edge flowing out from the vertex [phase], and conversely, the path transmitted by the directed edge flowing into a certain vertex @ is meaningless. If all the states of All directed edges that flow into or out of unnecessary vertices are unnecessary directed edges, and directed edges that connect between vertices in the on state are also unnecessary directed edges.In this way, unnecessary parts are omitted. In the remaining directed graph,
All paths from a vertex having an on state to a vertex connected to the ladder diagram output section are determined and each path is weighted (step 55). The path with the least weight is selected from among these paths (step S6). Next, the outgoing vertices in the selected least weight path.

The received vertices and the effective edges connecting them are determined (step 57). Here, the transmitting vertex is the vertex that has an on state on the path, the receiving vertex is the vertex into which the directed edge flowing out from the transmitting vertex flows, and the directed edge is the edge from the transmitting vertex to the receiving vertex.

That is, for example, as the minimum weight path (mouth) in FIG.
If is selected, the sending vertex O and the receiving vertex become ■, a directed acid.

Regarding the transmitting vertex, the receiving vertex, and the directed edge selected through the above steps 54 to S7, assuming that the directed edge is in a conductive state, the receiving vertex has an on state. Assuming that the edge is in a non-conducting state, the receiving vertex has an off state (step 511).

By recursively calling the subroutine "'5UBI" based on the assumptions of step S9 and step Sll (step 510), all possible states of the directed graph are simulated, and one of the possible paths in a certain state is simulated. The operation order can be determined by always selecting the path with the least weight.

Note that the output IA calculation in step S8 is performed when there is only a vertex to be connected to the ladder diagram output section as a transmission vertex, that is, when the vertex to be coupled to the ladder diagram output section is in an on state, or when the ladder diagram output section is in an ON state. When there is no path to the vertex that is connected to the diagram output section, that is, when it is found that the vertex that is connected to the ladder diagram output section can only be in the off state, the result is outputted in the ladder diagram output section. This is a calculation to be performed, and can be determined in step S5.

FIG. 9 is a diagram showing an example in which the order of operations between vertices for the directed graph in FIG. 6 is written out in the form of a two-branching tree based on the flowchart in FIG. 1. Therefore, step 521. S23. , S24. In S27 and 528, calculations between vertices are performed, and if the received vertex is on, the step in the left two-branching tree is executed, and if the received vertex is off, the step in the right two-branching tree is executed, and the output processing step is executed. s22
．． S2s, S2e, s29. When the processes at s3o and 531 are completed, the results of the logical operations on the digraph in FIG. 6 are obtained, and the next step can be carried out on the logical operations on the digraph.

However, in FIG. 9, steps with overlapping processing contents are, for example, steps 522, 525S26, and 525S26 of output processing.
529, 530 and S31. In this output processing step, an operation is performed to write the on/off state of the vertex (3) connected to the ladder diagram output section in FIG. 6 to the address g of the coil output contact in the ladder diagram in FIG. 5. Therefore, output processing step S22
．． Since exactly the same operations are performed in S25, 32B, S29, 530, and 531, these can be combined into one. This is because the directed graphs from which unnecessary vertices and unnecessary directed edges are removed in step S24 and step 528 become exactly the same.

In this way, FIG. 1O is a rewrite of FIG. 9 by combining the steps of performing the same operation on the same directed graph into one. In FIG. 1O, since duplication of operations is avoided, the number of execution objects of the sequence program does not increase more than necessary.

The method 7 for determining the calculation order of the ladder diagram input section according to the present invention is also useful when creating an object that is executed in software only by a CPU (Central Processing Unit) by providing a dedicated calculation circuit. Both are effective when creating objects to be executed by software.

FIG. 2 is a block diagram when the execution object created by the method of the present invention is realized in hardware, FIG. 3 is a detailed circuit diagram of the inter-vertex calculation unit 5 in FIG. 2, and FIG. 3 is an explanatory diagram of the contents of each signal in FIG. 3. FIG.

In the block diagram of FIG. 2, the execution object created by the method described above is stored in object memory 1.
The CPII 4 reads the object from the object memory 1 and executes the calculation. For inter-vertex calculations in execution objects, the logical value of the originating vertex is read out by the vertex logical value-time storage unit 2 and the inter-vertex calculation unit 5
0, and set the logic value of the contact on the directed side to the contact logic value - time storage unit 6
is read out and similarly set in the inter-vertex calculation unit 5. The inter-vertex calculation unit 5 performs a logical operation based on these, and uses the resulting logical value as the logical value of the received vertex as the vertex logical value -
The settings are reset to the time storage unit 2. Further, the I10 control i/roll unit 3 performs input/output control based on the contents of the contact logic value-time storage unit 6.

Next, the operation of the circuit diagram in FIG. 3 will be explained. In the figure, when the ENABLE signal is off,
In accordance with the timing of the clock (f; LOCK) signal, the logic value I10 of the transmitting vertex is sent to register 1 via the signal line IN.
1, and at the same time, the logical value of the a contact or b contact on the directed side is set in the register 10. Here, if the number of a-contacts or b-contacts is less than the number of elements of the register IO, the logical value °°1°° is set in the remaining register. After doing this, when the enable signal is turned on, the logical contents of register 10 and register 11 become stable, so the logical product of all the elements of register IO and register 11 is calculated by logical operation element 12, and the result is sent to the signal. It can be taken out from the line OUT.

(Effects of the Invention) As described above, according to the method and device for determining the operation order of the ladder diagram input section of the present invention, a ladder diagram is converted into a directed graph, and operations are performed preferentially from the path that takes the least time for logical operations. As a result, it can be expected that the processing time of the sequence program will be faster for the execution object as a whole. Furthermore, even in the worst case, the logical value of the vertex connected to the ladder diagram output section can always be obtained by calculating all paths of the directed graph, so the execution speed of the object is guaranteed to be faster than before.

[Brief explanation of drawings]

Figure 1 is a flowchart for determining the order of operations according to the present invention, Figure 2 is a block diagram for realizing the execution object created according to the present invention in hardware, and Figure 3 is a detailed circuit of the inter-vertex operation unit. Figure 4 shows the content of each signal in Figure 3, which is normally 1 = ON.

Claims (1)

[Claims] 1. The intersection of the vertical connection line of the ladder diagram representing the program contents and the boundary line of the input section and the output section with the horizontal connection line of the ladder diagram is set at the vertex having on/off information. The on/off information is placed on the directed side where the on/off information is transmitted only from left to right on the horizontal connection line, and the a contact and the b contact on the horizontal connection line are placed on the directed side. The ladder diagram is converted into a directed graph by corresponding to the gates that control the transmission of information, and information is transmitted between the vertices corresponding to the bus line, which is the leftmost vertical connection, and the vertices corresponding to the boundary line. All possible paths are extracted and weighted according to the complexity of the process, and the initial state is set to the on state for the vertices corresponding to the generatrix, and the off state for the other vertices. 1, and when the gate is in a conductive state, the information of the corresponding outflow side vertex is transmitted to the inflow side vertex.
By repeating the process of determining the transmission state of the passage for all gates in one passage in order from the passage with the lowest weight, the vertex corresponding to the boundary line between the input section and the output section is in the on state. 1. A method for determining the order of operations in a ladder diagram input section, characterized in that the method determines whether or not . 2. The calculation order determination method for a ladder input section according to claim 1, wherein a parameter proportional to the calculation time required for calculation in the path is adopted as the weight. 3. As a result of the calculation in the path, when a vertex that was previously in an OFF state changes to an ON state, the weighting in the path is redone.
A method for determining the operation order of the ladder diagram input section described in . 4. storage means for storing execution objects; vertex logical value storage means for storing logical values of transmitting and receiving vertices; and contact logical value storing means for storing logical values of contacts on directed edges; A logical operation is performed based on the logical value of the transmitting vertex stored in the vertex logical value storage means and the logical value of the corresponding contact point on the directed edge stored in the contact logical value storage means to determine the value of the receiving vertex. 1. An operation order determining device for a ladder diagram input section, characterized in that it is configured to include an inter-vertex operation means for calculating logical values, and a control means for controlling the entire operation. 5. The inter-vertex calculation means includes a register that stores the on/off state of the vertex on the side flowing to the directed edge as a logical value 1/0, and one or more a registers placed on the directed edge. The conduction/nonconduction state of each contact and b contact is set to a logical value of 1/0.
5. The ladder diagram according to claim 4, further comprising: one or more register groups for storing the data as a logical product; and logical operation means for inputting the logical values stored in the register and the register group to perform an AND operation. An operation order determining device for the input section.