JPH0385924A - Demodulation system immune from interference wave in direct modulation system - Google Patents

Abstract

PURPOSE:To attain normal data transmission even just after the reception of an interference wave by demodulating the output of a frequency discrimination circuit at a 1st demodulation circuit in the reception standby state, and after reception, demodulating the output of the circuit with a 2nd demodulation circuit at the reception of an input signal after a prescribed time. CONSTITUTION:An output of a frequency discrimination circuit 1 is fed to a 1st demodulation circuit 3 via a switch circuit 2 in the reception standby state. When a reception signal is received just after the reception of an interference wave, the switch circuit 2 is switched after a required delay time and the interference wave is restored to a center voltage with a normal input for the delay time. After a required delay time elapses, the output of the frequency discrimination circuit 1 is fed to a 2nd demodulation circuit 4. Even just after the reception of the interference wave, normal data transmission is attained.

Description

[Detailed Description of the Invention] [Summary] This invention relates to an anti-jamming wave demodulation system in the direct modulation system that makes it possible to eliminate the influence of interference waves when demodulating a signal received using the direct modulation system. The purpose of this is to enable normal data transmission even immediately after the signal is received, and the received signal using the direct modulation method is detected by a frequency discrimination circuit and further demodulated by a demodulation circuit including a capacitor. 1 on the output side of the frequency discrimination circuit.
The first demodulation circuit has a small time constant and the second demodulation circuit has a large time constant.
A demodulation circuit is provided, and in a reception waiting state before receiving the received signal, the output of the frequency discrimination circuit is demodulated by the ↓th demodulation circuit, and when the received signal is received, the frequency discrimination circuit is The output of the circuit is changed to the second one after the required delay time.
The demodulation circuit is configured to perform demodulation.

[Industrial Application Field] The present invention relates to an anti-interference wave demodulation system in a direct modulation system, which makes it possible to eliminate the influence of interference waves when demodulating a signal received using a direct modulation system.

For example, when transmitting data at a relatively high bit rate within a limited transmission band over a wireless line, a direct modulation method is used as a simple method.

This direct modulation method transmits a change in frequency by applying modulation to rOJ of data at a high frequency and modulating data "1" at a low frequency without using subcarriers.

In such a method, in order to be able to transfer unbalanced data containing many DC components, that is, data in which only "1" continues for a long time, instead of rlJ and rOJ being cursed alternately, A method has been adopted to enable data reproduction by increasing the time constant of the demodulated output of a frequency discrimination circuit on the receiving side.

Furthermore, in the frequency discriminator detection method used as a demodulation method, when an interference wave close to a target frequency that can be detected is added, a noise output corresponding to that frequency appears.

However, in fields that utilize radio frequencies, particularly in the field of mobile communications, the use of the 419 frequency or nearby frequencies is unavoidable, and their intensity often changes over the course of an hour.

In addition, recent wireless devices and surrounding areas 8! Many instruments use clock circuits, and harmonics are often generated near the target frequency.

[Prior Art] Now, in the above situation, a phenomenon that occurs when interference waves are added immediately before the actual communication is performed will be explained using FIG. 4.

FIG. 4 is a block diagram showing a conventional example. In FIG. 4, reference numeral 101 is an intermediate frequency amplification circuit, and this intermediate frequency amplification circuit 101 performs amplification in an intermediate frequency band.

1 and 02 are frequency discrimination circuits, and this frequency discrimination circuit 10
2 detects the output of the intermediate frequency amplification circuit 101.

Reference numeral 103 denotes a capacitor, and the capacitor 103 has a relatively large capacity.
IIljj2.

With this configuration, during normal reception, the capacitor 103 has a large capacity and the time constant of the circuit is large, so even if the received wave is unbalanced data containing many DC components, it can be demodulated without any problem. output.

[Problem to be solved by the invention] However, if the original communication is received while interference waves are being received immediately before the original communication, the time constant is set to be large. Therefore, it takes time to generate the original communication output, causing trouble.

In other words, unnecessary voltage due to interference waves is applied to the frequency discrimination circuit 1.
02 as the detection output of the frequency discrimination circuit 102.
Since the center voltage of the output deviates from the normal state, it takes time to recover, which interferes with data transmission under normal conditions.

The present invention attempts to solve such problems even immediately after the interference waves are received.

The object of the present invention is to provide an anti-interference demodulation method in a direct modulation method that allows normal data transmission.

[Means to solve the problem] FIG. 1 is a block diagram of the principle of the present invention.

In this Figure 1, 1 is a frequency discrimination circuit.

This frequency discrimination circuit 1 detects an intermediate frequency signal obtained from a received signal using a direct modulation method.

2 is a switch circuit, and this switch circuit 2 is switched to guide the output of the frequency discrimination circuit 1 to the first demodulation circuit 3 in a reception waiting state before receiving a reception signal;
When a received signal is received, the output of the two-frequency discrimination circuit 1 is switched to be guided to the second demodulation circuit 4 after a required delay time.

3 is a first demodulation circuit, and this first demodulation circuit 3 is
It demodulates the output from the frequency discrimination circuit 1 in the reception waiting state, and its time constant is configured to be small in order to reduce the influence of interference waves when transitioning to the state in which the intended reception signal is received. .

4 is a second demodulation circuit, and this second demodulation circuit 4 is
This is to demodulate the output from the frequency discrimination circuit 1 by reception (no. 4) while receiving the intended reception signal. In order to perform stable demodulation of data with unbalanced DC components, Its time constant is configured to be large.

[Function] In the anti-interference demodulation method in the direct modulation method of the present invention described above, in the reception waiting state in which the intended reception signal is not received, the output of the frequency discrimination circuit 1 is transferred to the first signal via the switch circuit 2. The signal is supplied to the demodulation circuit 3 of. This makes it possible to reduce the influence of interference waves when transitioning to a state in which the intended reception signal is received. In other words, when the intended reception signal is received immediately after receiving an interference wave, the switch circuit 2 is switched after a required delay time, but within this delay time the interference wave returns to the center voltage due to the normal input. It is.

After the above-mentioned required delay time has elapsed, the output of the frequency discrimination circuit 1 is supplied to the second demodulation circuit 4. Therefore, after that, stable demodulation of data with unbalanced DC components can be performed.

[Example] The present invention will be described in detail below with reference to one drawing.

Fig. 2 is a block diagram showing an embodiment of the present invention, and Fig. 3 is an electric circuit diagram showing main parts of the embodiment of the present invention. , this frequency discrimination circuit 1 receives an intermediate frequency signal obtained from a received signal using the direct modulation method (this signal is obtained by the intermediate frequency amplification circuit in the previous stage) and detects it.

2 is a switch circuit, and this switch circuit 2 is in an open state (OF) in order to guide the output on the frequency discrimination circuit to the demodulation circuit
When a received signal is received, after the required delay time set by the delay control circuit 6, the frequency discrimination circuit 1 is closed (ON state) in order to guide the output of the frequency discrimination circuit 1 to the second demodulation circuit 4. A semiconductor analog switch is used.

By the way, the above-mentioned delay control circuit 6 that controls the switch circuit 2 is composed of an amplifier 6a, a capacitor 6b, a resistor 6c, and a diode 6d, as shown in FIG. The delay time is determined by multiplying by the value. This delay time is set as a time sufficient to eliminate the deviation of the detected output voltage of the frequency discrimination circuit 1 from the center voltage due to the interference wave when the original received wave is received after the interference wave is received. Ru.

Further, the delay control circuit 6 is connected to a carrier squelch having a function of detecting whether or not the amplifier 6a has received the intended reception signal by the output from the intermediate frequency amplification circuit, and the resistor 6c is connected to a switch. It is connected to the control terminal C of the circuit 2. Therefore, in the reception waiting state before the original received signal is input to the intermediate frequency amplification circuit, the output from the carrier squelch is cut off, so the output is not output to the amplifier 6a. does not appear and the output through the resistor 6c is not input to the control terminal C of the switch circuit 2, so the input terminal i and the output terminal 0 of the switch circuit 2 are in a disconnected state fi (OFF state).

However, when the original received signal is input to the intermediate frequency amplification circuit, the output cutoff state in the carrier squelch is released, and the output is input to the resistor 6c forming the delay circuit, and the required signal is input to the intermediate frequency amplification circuit. After the delay time, an output appears in the delay side #circuit 6, thereby connecting the input terminal i of the switch 2 and the output terminal 0 (ON state).
I'll change it to 2.

3 is a demodulation circuit of the first construction, and this first demodulation circuit 3 is
It is constructed so that the output signal of the frequency discrimination circuit 1 is processed by a circuit with a small time constant, and is comprised of a small capacitance coupling capacitor 5.

4 is a second demodulation circuit, and this second demodulation circuit 4 is
It is constructed so that the output signal of the frequency discrimination circuit 1 is processed by a circuit with a large time constant, and includes a bias circuit 7 and a large-capacity bypass capacitor 8.

Here, the capacitance of the capacitor 8 is temporarily set to be about 1000 times the capacitance of the capacitor 5, for example.

Further, the bias circuit 7 has its input side connected to the switch circuit 2.
The point B, which is connected to the output side of the switch circuit 2 and the output terminal 0 of the switch circuit 2, is connected to the collector power supply via the resistor 7a and is grounded via the resistor 7b, so that the voltage at the point B is It is maintained in the required condition.

Further, the output side of the bypass capacitor 8 is connected to the output side of the coupling capacitor 5, and the demodulated signals outputted from these output sides are inputted to the next stage data processing circuit (not shown). It has become.

With the above-described configuration, in this embodiment, in the reception waiting state in which the original reception signal is not received, no control voltage is applied to the control terminal C of the switch circuit 2, and the input terminal j and the output terminal 0 are OF l? kept in condition.

This is because the carrier squelch connected to the input side of the delay control circuit 6 blocks the output from input interference waves whose frequency is slightly different from that of the original received signal, and the original received signal is This state is maintained until it is received.

In this state, as described above, the switch circuit 2 is in the OFF state, so input signals such as interference waves that are not the original received signals are output as some voltage in the frequency discrimination circuit 1. Since the time constant of the demodulation circuit 3 is small, it is absorbed by the coupling capacitor 5.

On the other hand, when the original received signal is input, the output cutoff state in the carrier squelch is released and the output of the carrier squelch is input to the delay control circuit 6. After the determined delay time, the control output is cursed, this control output is applied to the control terminal C of the switch circuit 2, and the switch circuit 2 is turned on. Therefore, due to interference waves, A
Even if the voltage at the point deviates from the center voltage, it will immediately return to the center voltage (within the delay time shown in L) by a normal input, and then the switch circuit 2 will turn on. This eliminates the influence of interference waves immediately after switching.

Then, the output of the 7-frequency discrimination circuit (with the switch circuit 2 in the ON state) is mostly output to the next-stage data processing circuit via the second demodulation circuit 4. Therefore, the bypass capacitor 8 performs demodulation with a large time constant, and even if the transmitted data is unbalanced and contains many DC components, normal demodulation can be performed without any problems.

In addition, the voltage at 8 points when the switch circuit 2 is turned on is as follows:
Since the bias circuit 3 makes it equal to the center voltage at point A, matching after switching is easy.

Also, during the required delay time after transitioning to the receiving state,
In order to eliminate the influence of interference waves, the signal is routed to the first demodulation circuit 3 side, which has a small time constant. Because the time constant of the demodulation circuit 3 is small, it may become difficult to reproduce low frequency components of data by direct modulation. Therefore, this problem is solved by adding bit synchronization in which "1" and "O" are transmitted alternately to the beginning of the data, and then transmitting the data portion. That is, the bit synchronization signal inserted at the beginning of data as shown in E has a small degree of imbalance in the DC component.

The first demodulation circuit 3 with a small time constant is used to eliminate the influence of interference waves during the required delay time after transitioning to the receiving state.
This is because even if a signal is passed to the other side, it can be sufficiently reproduced by the first demodulation circuit 3.

[Effects of the Invention] As detailed above, according to the anti-jamming wave demodulation method in the direct modulation system of the present invention, even if a jamming wave with a frequency close to the reception frequency that should be received is received, immediately after that, Since the demodulation of the original received signal is performed without any problem, there is an advantage that the adverse effects of interference waves can be avoided and highly reliable data transmission can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention. FIG. 2 is a block diagram showing an embodiment of the present invention. FIG. 3 is an electric circuit diagram showing the main configuration of an embodiment of the present invention; FIG. 4 is a block diagram showing a conventional example. In FIG. 6, 1 is a frequency discrimination circuit; 2 is a switch circuit, 3 is the demodulation circuit of the first stage, 4 is a second demodulation circuit; 5 is a coupling capacitor, 6 is a delay control circuit; 6a is an amplifier, 6b is a capacitor. 6c is resistance, 6d is a diode, 7 is a bias circuit, 7a and 7b are resistors, 8 is a bypass capacitor.

Claims (1)

[Claims] Frequency discrimination circuit (1)
In a device that detects the wave with A circuit (4) is provided, and in a reception waiting state before receiving the received signal, the output of the frequency discrimination circuit (1) is demodulated by the first demodulation circuit (3), and the output of the frequency discrimination circuit (1) is demodulated by the first demodulation circuit (3), and Anti-jamming demodulation in a direct modulation system, characterized in that when the frequency discriminator circuit (1) receives the signal, the second demodulation circuit (4) demodulates the output of the frequency discrimination circuit (1) after a required delay time. method.