JPH0388419A - Semiconductor relay circuit - Google Patents

Abstract

PURPOSE:To speed up the semiconductor relay circuit by connecting a photoconductive semiconductor element arranged to receive an optical signal of alight emitting diode between a drain and a gate of an output FET via a reverse flow block rectifier element. CONSTITUTION:A semiconductor element like a photo transistor(TR) 6 reaching a low impedance state in response to a light input is connected between a drain and a gate of an output FET 4 to form a path charting a gate-source capacitance of the output FET 4 from the load side via the semiconductor element. Moreover, since the reverse flow blocking rectifier element 7 connects in series with the semiconductor element, a current from a photovolatile diode array 2 is prevented from being leaked from the gate of the output FET 4 to the drain. Thus, the time required for increasing the gate-source voltage of the output FET 4 is reduced and the switching operation of the semiconductor relay circuit is speeded up.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor relay circuit using isolation by optical coupling.

[Prior art] Figure 6 shows a conventional semiconductor relay circuit (Japanese Patent Laid-Open No. 631539
1 and 6). The circuit configuration will be explained below. A vendor diode 1 is connected between relay input terminal 11+I2. A photovoltaic diode array 2 is optically coupled to the light emitting diode 1 . The positive electrode of the photovoltaic transistor 1 is connected via a resistor 3 to the gate of an output FET 4 of an NMOS type enhancer 1-mote. Further, the negative electrode of the photovoltaic diode array 2 is connected to the source of the output FET 4. A depression mode control F'ET5 is connected to the gate and source of the output FET4.
The source and drain of each are connected to each other. The gate of this control FET 5 is connected to the positive electrode of the photovoltaic diode array 2 . Relay output terminal 0 +,
02 is connected to the train and source of the output FET 4, respectively. Note that a Zener diode 8 is connected in parallel to the resistor 3 with the polarity shown.

A signal source S is connected as an external circuit via a resistor R between the relay input terminal and I2. Relay output terminal 0
．． ．． 02, a series circuit of a load Z and a DC power source E is connected as an external circuit with the polarity shown. Now, when an input current flows from the signal source S to the light emitting diode 1 through the resistor R, the light emitting diode 1 generates an optical signal. In response to this optical signal, the photovoltaic diode array 2 generates a current. This current flows to the resistor 3 between the source and train of the control transistor ET5, which is normally in a low impedance state.The voltage generated in the resistor 3
When the threshold voltage of T5 is exceeded, control FET5 enters a high impedance state. As a result, the current from the photovoltaic diode array 2 charges between the gate 1 and the source of the output FET 4, and the charging voltage is applied to the output FET 4.
When the threshold voltage of T4 is exceeded, the output FET
4 is in the on state, and relay output terminal 0. ．． 02 becomes conductive.

As a result, a load current flows through the load Z from the DC power supply E. Thereafter, a small amount of current flows through the resistor 3 between the source and drain of the control FET 5, and the bias voltage generated in the resistor 3 causes the control FE 5 to be maintained in a high impedance state.

The input current between relay input terminals I, I2 is cut off,
When the light signal from the light emitting diode (3) disappears, the output current from the photovoltaic diode array 2 disappears. Therefore, the gate-source voltage of the control FET 5 decreases, and the control FET 5 enters a low impedance state.
The charge accumulated in the gate-source capacitance of the output FET 4 is rapidly discharged through the control FET 5. As a result, the output FET 4 is turned off, and the relay output terminals 0 + and 02 are cut off.

In this circuit, in a steady state when the output FET 4 is turned on, even if the current flowing through the control FET i' 5 is small, if the value of the resistor 3 is increased, the control FET
Sufficient bias voltage can be obtained to keep T5 in the off state. However, if the value of the resistor 3 is increased, the time constant of the CR circuit that charges the gate-source capacitance during the transition period when the output FET 4 is turned on increases, so the turn-on time of the relay becomes longer. Therefore,
During the transition period until the gate-source voltage of the output FET 4 rises, the Zener tie auto 8 is made conductive to shorten the turn-on time of the relay.

On the other hand, as a conventional technique that aims to shorten the switching time by connecting the gate of the output FET to the train of the output FET via a semiconductor element controlled by optical input, Japanese Utility Model Application Publication No. 64-33228 discloses No. 4,390,790 exists.

First, in Japanese Utility Model Application Publication No. 64-33228, an optical input drive transistor that charges the gate capacitance of a MOS transistor in response to optical input includes a high-speed phototransistor that becomes conductive in response to optical input, and high-speed phototransistors 1 to 1.
It has been proposed to provide a circuit for supplying current from the controlled part to the gate of the MO8) transistor through conduction of the transistor, but a composition in which a rectifying element for blocking reverse current is connected in series to the phototransistor is not disclosed. It has not been.

Furthermore, U.S. Patent No. 4,390,790 discloses a circuit configuration in which the drain and source of a bias MOSFET controlled by optical input are connected between the drain and source of an output MO8FET. has been disclosed, but
There is no disclosure of a composition in which a rectifying element for blocking backflow is connected in series to a MO3FET for bias.

[Invention or problem to be solved M] In the prior art shown in FIG. 6, the current used to increase the gate-source voltage of the output FET 4 is supplied only from the photovoltaic diode array 2. has been done. Therefore, if the magnitude of the input current is constant, the turn-on time of the relay is determined by the capability of the photovoltaic diode array 2 and cannot be made any faster.

Therefore, as disclosed in Japanese Utility Model Application Publication No. 64-33228 or U.S. Pat.
It is conceivable to connect an ET between the drain and gate of the output FET to accelerate the rise in the voltage between the gate and source of the output FET.

However, the techniques disclosed in the above two publications are difficult to implement. This is because a phototransistor whose base region has charges injected by optical input cannot block reverse current. Also, the MOSFET has a drain
Since an anti-parallel PN junction diode is parasitic between the sources, reverse current cannot be blocked. Therefore, when these semiconductor elements are connected between the drain and gate of the output FET, there is a path for current to escape from the gate of the output FET to the train, so the output FET
When ET is fully turned on and the train-source voltage is essentially zero, current from the photovoltaic diode array attempts to flow between the drain and source of the output FET. Therefore, the on-resistance of the output FET is quite large, and even in a completely on state, the output FET can achieve the effect of speeding up, and its train voltage is extremely high (usually about 5 V or more) higher than the gate voltage. This is only possible in rare cases, and there is a problem in that the operating range is essentially limited.

The present invention has been made in view of these points, and its purpose is to shorten the time required for the voltage between the gate and source of the output FET to rise, thereby realizing high-speed semiconductor relay circuits. There is a particular thing.

[Means for Solving the Problems] In the present invention, in order to solve the above problems, the first
As shown in the figure, a light emitting diode 1 that generates an optical signal in response to an input signal, a photovoltaic tie-auto array 2 arranged to receive the optical signal of the light emitting diode (2),
An output F E 'F4 to which the photovoltaic force of the photovoltaic diode array 2 is applied between the gate and source to switch between a conducting state and a non-conducting state between the drain and source, and an output F
In a semiconductor relay circuit including a control circuit 10 that forms a discharge path for accumulated charges between the gate and source of the E The present invention is characterized in that a conductive type semiconductor element is connected between the drain and gate of the output FET 4 via a rectifying element 7 for blocking backflow.

Further, as shown in FIG. 4, when the photovoltaic force of the photovoltaic diode array 2 is applied between the gate and source of the output FET 4 via the resistor 3, the photovoltaic diode array 2 A semiconductor element such as a transistor 16 that is biased to a low impedance state by the voltage generated across the resistor 3 when a photovoltaic force is generated by the transistor 16 to form a charging path for the accumulated charge between the gate and source of the output FET 4, It may be connected in place of the phototransistor 6.

In addition, as shown in FIG. 2 or FIG. 5, the current limiting resistor 9
It is preferable to connect the rectifying element 7 in series with the rectifying element 7 for blocking backflow.

[Function] According to the present invention, as described above, semiconductor elements such as the photo transistor 16 and the transistor 16, which become in a low impedance state in response to optical input, are connected to the output FET.
Since it is connected between the drain and the gate I of the output FET 4, a path can be formed to charge the gate-source capacitance of the output FET 4 from the load side via this semiconductor element. Further, since the rectifying element 7 for blocking backflow is connected in series to the semiconductor element, it is possible to prevent the current from the photovoltaic diode array 2 from leaking from the gate to the drain of the output FET 4. Therefore, output FET4
The time required for the gate-source voltage to rise can be shortened, and the switching operation of the semiconductor relay circuit can be speeded up.

[Embodiment] FIG. 1 is a circuit diagram of an embodiment of the present invention. The circuit configuration will be explained below. Relay input terminals I,, I2
A light emitting diode 1 is connected between them. A photovoltaic diode array 2 is optically coupled to the light emitting diode 1 . The positive electrode of the photovoltaic diode array 2 is
NMOS type enhancement mode output FE
Connected to the gate of T4. Further, the negative electrode of the photovoltaic diode array 2 is connected to the source of the output FET 4. Between the gate and source of output FET4,
A control circuit 10 is connected. This control circuit 10 is
When the photovoltaic diode array 2 generates photovoltaic force, it is in a high impedance state, and when it stops generating photovoltaic force, it is in a low impedance state! It is structured in such a way that it follows the sequence.

Output FET 4 is connected to relay output terminals 0 + and 02.
The drain and source of each are connected to each other.

The above circuits are housed in one package.

A series circuit of a DC power supply V, a switch Q, and a resistor R is connected between relay input terminals II and I2 as an external circuit. Relay output terminal 0. ．． 02, a series circuit of a load Z and a DC power source E is connected as an external circuit with the polarity shown. Now, when the switch Q is turned on and an input current flows from the DC power supply 2 to the light emitting diode 1 through the resistor R, the light emitting diode 1 generates an optical signal. In response to this optical signal, the photovoltaic diode array 2 generates a current.

At this time, since the control circuit 10 becomes a high impedance moat, the current from the photovoltaic diode array 2 is
Charge the gate-source capacitance of output FET4. In addition, since the phototransistor RO receives the optical signal from the light emitting tie 1 and becomes conductive, the load Z is transferred from the DC power supply E to the load Z.
Current also flows through the relay output terminal O diode 7, the phototransistor 6, the gate-source capacitance of the output transistor 4, and the relay output terminal 02. Since this current also charges the gate-source capacitance of the output FET 4, the rise in the gate-source voltage of the output FET 4 is accelerated. The gate-source voltage of output FET4 is the output FE
When the threshold voltage of T4 is exceeded, output FET4 turns on, and relay output terminal 0. ．． 02 becomes conductive. As a result, a load current flows through the load Z from the DC power supply E. Note that even if the output FET 4 is completely turned on and the drain-source voltage is almost zero, the current from the photovoltaic diode array 2 is still It does not flow between the drain and source of the output FET 4 via the photo 1 to the transistor.

Next, switch Q is turned off, and relay input terminals I,...
When the input current between the photovoltaic diode arrays 2 and 12 is cut off and there is no light signal from the light emitting diodes 1 to 1, the photovoltaic diode array 2
There is no output current from the. At this time, since the control circuit 10 is in a low impedance state, the output FET
The charge N multiplied in the gate 1 to source capacitance of No. 4 is rapidly discharged through the control circuit 10. by this,
Output FET4 is turned off, and relay output terminal 0.
．． 02 is cut off.

FIG. 2 shows a modification of the above embodiment, in which a current limiting resistor 9 is connected in series to a rectifying element 7 for blocking backflow. In this circuit configuration, the response time of the output FET 4 was measured while changing the value of the current-limiting resistor 9.
The results shown in FIG. 3 were obtained. That is, the value of the current-limiting resistor 9 may be appropriately selected depending on the characteristics of other circuit elements, or, for example, in the example shown in FIG.
The value of 0.5 to 1. It will be understood that when the range is set to OMΩ, the turn-on response time 'l'on;/J·48 μS can be stably obtained, and the turn-off response time Toff can be stably obtained around 36 μS. Even if this is later than the turn-off time of the phototransistor 6, which is a semiconductor element for accelerating the rise in the gate-source voltage of the output FET 4, or the time required to lower the impedance of the control circuit 10, The current flowing from the drain of the output FE5 T4 to the gate 1 at turn-off is limited by the current limiting resistor 9.
This is to prevent the voltage between the gate and source of the output FET 4 from decreasing.

In the semiconductor relay circuit shown in FIG. 1 or 2, a photoconductive semiconductor element is used as a photoconductive semiconductor element to form a charging path from the load side of the gate I to source capacitance of the output FET 4. Although the transistor 6 is used, a photothyristor, a photodiode, etc. may also be used. Particularly, when photosilisk is used, the semiconductor element and the rectifying element for blocking backflow can be realized in one element.

FIG. 4 is a circuit diagram of another embodiment of the present invention.

The circuit of this embodiment omits the Zener diode 8 connected in parallel with the resistor 3 in the conventional example shown in FIG. Connect the emitter to F for output.
It is connected to the gate of the ET4, and its collector is connected to the drain of the output FET4 via a rectifying element 7 for blocking backflow. The rest of the circuit configuration is the same as the conventional example 6 shown in FIG.

The operation of this embodiment will be explained below. When an input current flows through the light emitting diode 1, the light emitting diode 1 generates a light signal. In response to this optical signal, the photovoltaic tie auto array 2 generates a current.

This current flows through the control F, which is normally in a low impedance state.
Flows into resistor 3 via the source and train of ET5.

When the voltage generated by the resistor 3 exceeds the threshold voltage of the control FET 5, the control FET 5 enters a high impedance state. As a result, the current from the photovoltaic diode array 2 charges between the cable 1 and the source of the output FET 4.

Furthermore, the voltage generated by the resistor 3 forward biases the base and emitter of the transistor 16, so that the collector and emitter of the transistor 16 become conductive. As a result, from DC power supply E to load 2, relay output terminal 01,
A charging current flows between the gate and source of the output FET'4 via the rectifying element 7 for blocking reverse current and the collector and emitter of the transistor 16. Therefore, the output FET
4-7 The gate-source voltage rises quickly. When this voltage exceeds the threshold voltage of output FET4,
Output FET4 turns on and relay output terminal 0.
．． 02 becomes conductive. Thereafter, a small amount of current flows through the resistor 3 between the source and drain of the control FET 5, and the bias voltage generated in the resistor 3 keeps the control FET 5 in a high impedance state. Note that after the output FET 4 is completely turned on, its drain-source voltage becomes almost zero, so the current from the photovoltaic diode array 2 flows through the transistor 1.
Output FE via PN junction between base and collector of 6
It tries to flow between the drain and source of T4, but since this path is provided with a rectifying element 7 for blocking backflow,
No current flows.

The input current between relay input terminals It and I2 is cut off,
When the light signal from the light emitting diode 1 disappears, the output current from the photovoltaic diode array 2 disappears. At this time, the transistor 16 is reverse biased between the gate and the emitter of the output FET 4, so its collector and emitter are reverse biased.
There is no conduction between the emitters. Also, due to the disappearance of the photovoltaic force, the gate-source voltage of the control FET5 decreases, so the control FET5 becomes a low impedance state and the output 1? The charge accumulated in the gate-source capacitance of ET4 is lfi! It is rapidly discharged through the control FET5.

As a result, output FET 4 is turned off, and relay output terminal 0. ．． 02 is cut off.

FIG. 5 shows a modification of the above embodiment, in which a current limiting resistor 9 is connected in series to a rectifying element 7 for blocking backflow. It is clear that the same effect as the circuit not shown in Fig. 2 can be obtained in this circuit as well.9 In addition, in the semiconductor relay circuit shown in Fig. 4 or 5, the voltage generated across the resistor 3 Although an NPN type bipolar transistor 16 is used as a semiconductor element that is forward biased by, a junction type or MOS type FET may be used, or a thyristor may be used. In particular, if a reverse blocking three-terminal thyristor is used, the semiconductor element and the rectifying element can be implemented in one element.

[Effects of the Invention] In the semiconductor relay circuit of the present invention, the current used to increase the gate-source voltage of the output FET is supplied from the photovoltaic diode array optically coupled to the light emitting diode on the input side. Not only that, it is also supplied from the load side via the rectifying element and semiconductor element for blocking reverse current, so
This has the effect of shortening the time required for the voltage between the gate and source of T to rise and speeding up the switching operation. Furthermore, due to the presence of the rectifying element for blocking reverse current, the present invention can be implemented even when the train voltage when the output FET is turned on is lower than the gate voltage, and the operating range is reduced compared to the conventional technology. The effect is that it can be expanded dramatically.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram of a modified example of the same, FIG. 3 is an explanatory diagram of the operation of the same, and FIG. 4 is a circuit of another embodiment of the present invention. 5 is a circuit diagram of a modified example of the same as the above, and FIG. 6 is a circuit diagram of a conventional example. 1 is a light emitting diode array, 2 is a photovoltaic diode array,
3 is a resistor, 4 is an output FET, and 5 is a control FET.
, 6 is a phototransistor, 7 is a rectifier, 9 is a resistor,
10 is a control circuit, and 1G is 1 to run sister.

Claims (4)

[Claims] (1) A light-emitting diode that generates an optical signal in response to an input signal, a photovoltaic diode array arranged to receive the optical signal of the light-emitting diode, and a gate gate for the photovoltaic force of the photovoltaic diode array. A semiconductor relay that includes an output FET to which a conductive state and a non-conductive state are applied between the drain and the source by applying an electric current between the sources, and a control circuit that forms a discharge path for accumulated charges between the gate and source of the output FET. In the circuit, a photoconductive semiconductor element arranged to receive an optical signal from the light emitting diode is connected between the drain and gate of the output FET via a rectifying element for blocking backflow. Semiconductor relay circuit. (2) A light emitting diode that generates a light signal in response to an input signal, a photovoltaic diode array arranged to receive the light signal of the light emitting diode, and a resistor connected in series with the photovoltaic diode array. an output FET to which the photovoltaic force of the photovoltaic diode array is applied between the gate and source via the resistor to switch between a conductive state and a non-conductive state between the drain and source;
and a control circuit for forming a discharge path for accumulated charge between sources, the semiconductor relay circuit is biased to a low impedance state by a voltage generated across the resistor when a photovoltaic diode array generates a photovoltaic force,
A semiconductor relay circuit characterized in that a semiconductor element forming a charging path for accumulated charges between the gate and source of the output FET is connected between the drain and gate of the output FET via a rectifying element for blocking reverse flow. . (3) The control circuit is biased to a high impedance state by a voltage generated across the resistor when a photovoltaic force is generated by the photovoltaic diode array, and changes to a low impedance state when no bias is applied to the gate of the output FET. - The semiconductor relay circuit according to claim 1 or 2, further comprising a control FET that forms a discharge path for accumulated charge between sources. (4) Claim 1, 2 or 3, characterized in that a current limiting resistor is connected in series to the rectifying element for blocking backflow.
The semiconductor relay circuit described.