JPH0389600U

JPH0389600U -

Info

Publication number: JPH0389600U
Application number: JP15153289U
Authority: JP
Priority date: 1989-12-27
Filing date: 1989-12-27
Publication date: 1991-09-12

Description

[Brief explanation of the drawing]

第１図は本考案の半導体メモリ装置の要部回路
図、第２図は従来の半導体メモリ装置の要部回路
図である。１，１０……ＭＯＳＦＥＴ、２，１１……メモ
リセル列、３，４，１２……選択トランジスタ、
５，１３……ビツト線、６，１４……ワード線、
７，１６……ブロツク選択線、１５……接地線。 FIG. 1 is a circuit diagram of a main part of a semiconductor memory device of the present invention, and FIG. 2 is a circuit diagram of a main part of a conventional semiconductor memory device. 1, 10...MOSFET, 2, 11...memory cell column, 3, 4, 12...selection transistor,
5, 13...bit line, 6,14...word line,
7, 16...Block selection line, 15...Grounding line.

Claims

[Claims for Utility Model Registration] A word in which a plurality of memory cell transistors are connected in series to form a memory cell column, and the gates of opposing memory cell transistors of a pair of memory cell columns arranged facing each other are common. In a semiconductor memory device in which one end of the pair of memory cell columns is connected to a common bit line via a selection transistor and the other end is grounded, a pair of memory cells from a plurality of memory cell columns are connected to a common bit line. a first selection means for selecting a column and connecting one end of the memory cell column to the bit line; and a first selection means for selecting one of the pair of memory cell columns selected by the selection means; A semiconductor memory device comprising: second selection means for grounding the other end.