JPH038963Y2 - - Google Patents
Info
- Publication number
- JPH038963Y2 JPH038963Y2 JP19774484U JP19774484U JPH038963Y2 JP H038963 Y2 JPH038963 Y2 JP H038963Y2 JP 19774484 U JP19774484 U JP 19774484U JP 19774484 U JP19774484 U JP 19774484U JP H038963 Y2 JPH038963 Y2 JP H038963Y2
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- camera
- video signal
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910000831 Steel Inorganic materials 0.000 claims description 10
- 238000005259 measurement Methods 0.000 claims description 10
- 239000010959 steel Substances 0.000 claims description 10
- 238000010586 diagram Methods 0.000 description 6
- 230000010354 integration Effects 0.000 description 4
- 230000000630 rising effect Effects 0.000 description 3
- 230000004069 differentiation Effects 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Landscapes
- Length Measuring Devices By Optical Means (AREA)
Description
【考案の詳細な説明】
〔産業上の利用分野〕
本発明は、鋼管製造プロセスにおける端面形状
検査に必要なルートフエース計測装置に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a root face measuring device necessary for end face shape inspection in a steel pipe manufacturing process.
鋼管製造工程を経て製造された鋼管の面取后の
端面は第3図に示すように斜面部と平面部からな
り、この平面部がルートフエースと呼ばれ、その
測定は端面形状検査の重要な項目である。なお斜
面部の外面側はパイプ同志の溶接開先となり、内
面側は溶接したパイプ相互間に段ずれが生じたと
きの流体抵抗増大防止用である。
The end face of a steel pipe manufactured through the steel pipe manufacturing process after chamfering consists of a sloped part and a flat part, as shown in Figure 3. This flat part is called the root face, and its measurement is an important part of end face shape inspection. It is an item. The outer surface of the sloped surface serves as a welding groove between the pipes, and the inner surface serves to prevent an increase in fluid resistance when a step shift occurs between the welded pipes.
光学的な手法によるこのルートフエースの測定
には図示のように投光器と、CCDなどのイメー
ジセンサカメラを用い、鋼管10を回転させなが
ら各回転位置でのルートフエース(直径)を測定
する。カメラはパイプ端面を第3図の状態で眺
め、半径方向の走査をする。従つてそのビデオ出
力は第4図(3)の如き波形を有する。これを従来は
第2図の如き回路で処理してルートフエース測定
を行なつていた。 To measure this root face using an optical method, as shown in the figure, a floodlight and an image sensor camera such as a CCD are used to measure the root face (diameter) at each rotational position while rotating the steel pipe 10. The camera views the end face of the pipe as shown in Figure 3 and scans in the radial direction. Therefore, the video output has a waveform as shown in FIG. 4(3). Conventionally, this has been processed using a circuit as shown in FIG. 2 to measure the root phase.
第2図で12は上記カメラ、14は比較器、1
6は基準値設定器、18はアンドゲート、20は
カウンタ、22はラツチメモリ、24は表示器及
び又は記録器、26はクロツク発生器、28は分
周器、30,32はワンシヨツト回路である。カ
メラ12の1列に並べられた撮像素子の数をnと
すると、nクロツクを与えることにより第4図(3)
の如き1ライン分ビデオ出力が得られ、鋼管10
の各回転位置でかゝる処理をすることにより、各
回転位置における1ライン分ビデオ出力が得られ
る。分周器28はクロツク発生器26が出力する
クロツクを1/nに分周し、ワンシヨツト回路3
0は分周器28の出力の例えば立上り時に所定幅
の出力を生じ、これをスタートパルスSPとして
カメラ12に入力する。カメラ12は該パルス
SPを受けて上記ビデオ信号の出力を開始する。
スタートパルスSPはまたワンシヨツト回路32
に入つてカウンタ20のリセツトパルスRPを発
生させ、またラツチメモリ22に入つて該リセツ
トが行なわれる直前のカウンタ20の内容をラツ
チメモリへ取込ませる。 In Fig. 2, 12 is the camera, 14 is a comparator, 1
6 is a reference value setter, 18 is an AND gate, 20 is a counter, 22 is a latch memory, 24 is a display and/or recorder, 26 is a clock generator, 28 is a frequency divider, and 30 and 32 are one-shot circuits. If the number of image sensors arranged in one row of the camera 12 is n, then by giving n clocks, as shown in Fig. 4(3),
One line of video output like this can be obtained, and the steel pipe 10
By performing such processing at each rotational position, one line of video output at each rotational position can be obtained. The frequency divider 28 divides the frequency of the clock output by the clock generator 26 to 1/n, and outputs the one-shot circuit 3.
0 produces an output of a predetermined width at the rise of the output of the frequency divider 28, and inputs this to the camera 12 as a start pulse SP. The camera 12
Upon receiving SP, it starts outputting the video signal.
The start pulse SP is also a one-shot circuit 32.
The counter 20 reset pulse RP is entered into the counter 20, and the counter 20 reset pulse RP is entered into the latch memory 22, and the contents of the counter 20 immediately before the reset is taken into the latch memory.
カメラ12がスタートパルスSPを受けてビデ
オ信号の出力を開始すると、これは比較器14に
おいて設定器16からの基準値と比較され、ビデ
オ信号が基準値以上のとき比較器14はH(ハイ)
レベル出力を生じ、アイドゲート18を開く。従
つてクロツク発生器26からのクロツクがアンド
ゲート18を通つてカウンタ20に入り、このカ
ウンタはスタートパルスSPに続いて発生するリ
セツトパルスRPにより零にクリヤされているか
ら該クロツクを零より計数開始する。ビデオ信号
が基準値以下になるとアンドゲート18は閉じ、
カウンタへのクロツク入力はやむ。従つてカウン
タ20はそれ迄の計数状態にとどまり、やがて次
のスタートパルスSPが発生するとき該計数値を
ラツチメモリ22へ送る。このメモリ22の内容
は表示器/記録器24で表示/記録される。 When the camera 12 receives the start pulse SP and starts outputting a video signal, the comparator 14 compares this with a reference value from the setting device 16, and when the video signal is equal to or higher than the reference value, the comparator 14 outputs an H (high) signal.
A level output is generated and the eye gate 18 is opened. Therefore, the clock from the clock generator 26 passes through the AND gate 18 and enters the counter 20, and since this counter has been cleared to zero by the reset pulse RP generated following the start pulse SP, the clock starts counting from zero. do. When the video signal falls below the reference value, the AND gate 18 closes.
Clock input to the counter stops. Therefore, the counter 20 remains in the counting state up to that point, and sends the counted value to the latch memory 22 when the next start pulse SP is generated. The contents of this memory 22 are displayed/recorded on a display/recorder 24.
この従来回路ではルートフエース測定精度は余
り高くない。即ち鋼管端面の周辺部は斜面になつ
ており、この影響でカメラ12が出力するビデオ
信号は第4図3に示すように立上り/立下り部が
鈍つている。そこで基準値の設定の仕方によつて
カウンタ計数値が大きく異なり、正確なルートフ
エースが把握しにくい。
With this conventional circuit, the root phase measurement accuracy is not very high. That is, the periphery of the end face of the steel pipe is sloped, and as a result of this, the video signal output from the camera 12 has slow rising and falling parts, as shown in FIG. 4. Therefore, the counter count value varies greatly depending on how the reference value is set, making it difficult to determine the exact route phase.
ルートフエースと斜面部との境界は折曲部を形
成しており、ビデオ信号の振幅は大きな変化をす
る。本考案はこの点に着目し、ビデオ信号の波形
を成形して上記境界部を強調し、正確なルートフ
エース測定を可能にしようとするものである。 The boundary between the root face and the slope portion forms a bend, and the amplitude of the video signal changes greatly. The present invention focuses on this point and attempts to shape the waveform of the video signal to emphasize the boundary portion, thereby enabling accurate root phase measurement.
本考案は、鋼管の端面を撮像するカメラと、該
カメラが出力する1ライン分ビデオ信号を基準値
と比較し、該ビデオ信号が基準値以上のときゲー
ト開放出力を生じる比較器と、開放された該ゲー
トを通つて入力するクロツクを計数し、ルートフ
エース測定出力を生じるカウンタとを備える電縫
管のルートフエース計測装置において、該カメラ
が出力するビデオ信号を滑らかにする遅延型積分
回路と、該積分回路の出力を微分する第1微分回
路と、該第1微分回路の出力を微分する第2微分
回路と、前記遅延型積分回路の出力と第2微分回
路の出力との差を求めそれを前記比較器への入力
とする減算回路とを設けたことを特徴とするもの
である。
The present invention consists of a camera that images the end face of a steel pipe, a comparator that compares one line of video signal output by the camera with a reference value, and generates a gate open output when the video signal is greater than or equal to the reference value; A delay-type integration circuit for smoothing a video signal outputted by the camera in a root phase measurement device for an ERW tube, which includes a counter that counts clocks input through the gate and generates a root phase measurement output; A first differentiating circuit that differentiates the output of the integrating circuit, a second differentiating circuit that differentiates the output of the first differentiating circuit, and determining the difference between the output of the delay type integrating circuit and the output of the second differentiating circuit. The present invention is characterized in that it is further provided with a subtraction circuit which inputs .
第1図は本考案の実施例を示し、第2図と同じ
部分には同じ符号が付してある。両者を対比すれ
ば明らかなように本考案ではカメラ12が出力す
るビデオ信号の回路に遅延積分回路(ローパスフ
イルタ)34、第1微分回路36、第2微分回路
38、および減算器40を挿入する点が従来回路
と異なる。
FIG. 1 shows an embodiment of the present invention, and the same parts as in FIG. 2 are given the same reference numerals. As is clear from comparing the two, in the present invention, a delay integration circuit (low-pass filter) 34, a first differentiation circuit 36, a second differentiation circuit 38, and a subtracter 40 are inserted into the circuit for the video signal output from the camera 12. This point differs from conventional circuits.
第4図の波形図を参照しながら第1図の回路の
動作を説明するに、カメラ12はCCD(Charge
Coupled Device)としてその個々の撮像素子は、
該素子に入射した光量に対応する電荷を生じ、該
電荷が直列に転送され、出力端で電位変化とな
り、電位変化がビデオ信号となるから、該ビデオ
信号は第4図3のように多段階段波状になる。遅
延型積分回路34はこれを第4図4に示すように
滑らかにし後続の微分処理に支障がないようにす
る。第1微分回路36はこれを微分して第4図5
の如き出力を生じ、第2微分回路38はこれを更
に微分して第4図6の如き出力を生じる。減算器
40は遅延型積分回路34の出力と第2微分回路
38の出力との差をとり、第4図7に示す出力を
生じる。第4図7は第4図4と比べれば明らかな
ように鋭い立上り、立下りを見せており、立上
り/立下り部は前記境界に対応する。これを比較
器14において適当な基準値と比較し、第4図8
の出力を得る。この第4図8の比較器出力でアン
ドゲート18を開き、この間のクロツク数をカウ
ンタ20で計数すれば、正確なルートフエースの
測定ができる。立上り/立下りが鋭くなつている
(直立状態になつている)ので基準値が若干不適
切であつても大きな測定誤差は生じない。第4図
9はカウンタ20でクロツクが計数される状態を
説明する図である。 To explain the operation of the circuit shown in FIG. 1 with reference to the waveform diagram shown in FIG.
The individual image sensors are
A charge corresponding to the amount of light incident on the element is generated, and the charge is transferred in series, resulting in a potential change at the output end, and the potential change becomes a video signal, so the video signal is processed in multiple stages as shown in Figure 4.3. Become wavy. The delay type integration circuit 34 smooths this as shown in FIG. 4 so that the subsequent differential processing is not hindered. The first differentiating circuit 36 differentiates this and the result is shown in FIG.
The second differentiating circuit 38 further differentiates this to produce an output as shown in FIG. 4. The subtracter 40 takes the difference between the output of the delay type integrating circuit 34 and the output of the second differentiating circuit 38, and produces the output shown in FIG. 4. When compared with FIG. 4, FIG. 4 clearly shows sharp rises and falls, and the rising/falling portions correspond to the boundaries. This is compared with an appropriate reference value in the comparator 14, and as shown in FIG.
get the output of If the AND gate 18 is opened by the output of the comparator shown in FIG. 4 and the counter 20 counts the number of clocks during this period, the root phase can be accurately measured. Since the rising and falling edges are sharp (standing upright), no large measurement error will occur even if the reference value is slightly inappropriate. FIG. 4 is a diagram illustrating the state in which clocks are counted by the counter 20.
〔考案の効果〕
以上説明したように本考案によればルートフエ
ースと斜面部の分離が容易、正確に行なえ、高精
度のルートフエース測定が可能になる。[Effects of the Invention] As explained above, according to the present invention, the root face and the slope portion can be easily and accurately separated, and highly accurate root face measurement becomes possible.
第1図は本考案の実施例を示すブロツク図、第
2図は従来例を示すブロツク図、第3図はルート
フエース測定要領を説明する図、第4図は動作説
明用の波形図である。
図面で10は鋼管、12はカメラ、14は比較
器、20はカウンタ、34は遅延型積分回路、3
6,38は第1,第2微分回路、40は比較器で
ある。
Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram showing a conventional example, Fig. 3 is a diagram explaining the route phase measurement procedure, and Fig. 4 is a waveform diagram for explaining the operation. . In the drawing, 10 is a steel pipe, 12 is a camera, 14 is a comparator, 20 is a counter, 34 is a delay type integration circuit, 3
6 and 38 are first and second differentiating circuits, and 40 is a comparator.
Claims (1)
力する1ライン分ビデオ信号を基準値と比較し、
該ビデオ信号が基準値以上のときゲート開放出力
を生じる比較器と、開放された該ゲートを通つて
入力するクロツクを計数し、ルートフエース測定
出力を生じるカウンタとを備える電縫管のルート
フエース計測装置において、 該カメラが出力するビデオ信号を滑らかにする
遅延型積分回路と、該積分回路の出力を微分する
第1微分回路と、該第1微分回路の出力を微分す
る第2微分回路と、前記遅延型積分回路の出力と
第2微分回路の出力との差を求めそれを前記比較
器への入力とする減算回路とを設けたことを特徴
とする鋼管のルートフエース計測装置。[Claim for Utility Model Registration] Comparing a camera that images the end face of a steel pipe and one line of video signal outputted by the camera with a reference value,
Root phase measurement of an ERW pipe, comprising a comparator that generates a gate open output when the video signal is above a reference value, and a counter that counts clocks input through the opened gate and generates a root phase measurement output. The apparatus includes: a delay-type integrating circuit that smooths a video signal output by the camera; a first differentiating circuit that differentiates the output of the integrating circuit; and a second differentiating circuit that differentiates the output of the first differentiating circuit; A steel pipe root phase measuring device, comprising: a subtraction circuit that calculates the difference between the output of the delay type integrating circuit and the output of the second differentiating circuit and inputs the difference to the comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19774484U JPH038963Y2 (en) | 1984-12-27 | 1984-12-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19774484U JPH038963Y2 (en) | 1984-12-27 | 1984-12-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61112209U JPS61112209U (en) | 1986-07-16 |
| JPH038963Y2 true JPH038963Y2 (en) | 1991-03-06 |
Family
ID=30756203
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19774484U Expired JPH038963Y2 (en) | 1984-12-27 | 1984-12-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH038963Y2 (en) |
-
1984
- 1984-12-27 JP JP19774484U patent/JPH038963Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61112209U (en) | 1986-07-16 |
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