JPH039045U - - Google Patents
Info
- Publication number
- JPH039045U JPH039045U JP6907889U JP6907889U JPH039045U JP H039045 U JPH039045 U JP H039045U JP 6907889 U JP6907889 U JP 6907889U JP 6907889 U JP6907889 U JP 6907889U JP H039045 U JPH039045 U JP H039045U
- Authority
- JP
- Japan
- Prior art keywords
- channel
- empty
- transfer request
- dma
- dma transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004044 response Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000010365 information processing Effects 0.000 description 2
Landscapes
- Bus Control (AREA)
Description
図面は本考案の一実施例を説明するためのもの
で、このうち第１図はＤＭＡチヤネル制御装置を
使用した情報処理装置の構成の一例を表わしたブ
ロツク図、第２図はデバイス側の動作の流れの概
要を表わした流れ図、第３図はＤＭＡ転送要求テ
ーブルの構成の一例を表わした平面図、第４図は
ＤＭＡチヤネル制御装置内のＤＭＡスケジユーラ
の制御の様子を表わした流れ図、第５図はこの割
り込み発生時のＤＭＡスケジユーラの動作を表わ
した流れ図、第６図は第４図のステツプでＤＭ
Ａ転送待ちキユーに登録したＤＭＡ転送要求のキ
ヤンセルが行われる場合の制御の様子を表わした
流れ図である。
１１……ＣＰＵ、１２……ＲＡＭ、１３……Ｄ
ＭＡコントローラ、１７……磁気デイスク、１８
……ＣＲＴ、３１……ＤＭＡ転送要求テーブル。
The drawings are for explaining one embodiment of the present invention. Among these, Fig. 1 is a block diagram showing an example of the configuration of an information processing device using a DMA channel control device, and Fig. 2 is a block diagram showing an example of the configuration of an information processing device using a DMA channel control device. 3 is a plan view showing an example of the configuration of a DMA transfer request table, FIG. 4 is a flow chart showing the state of control of the DMA scheduler in the DMA channel control device, and FIG. The figure is a flowchart showing the operation of the DMA scheduler when this interrupt occurs.
12 is a flowchart showing the state of control when a DMA transfer request registered in the A transfer queue is canceled. 11...CPU, 12...RAM, 13...D
MA controller, 17...magnetic disk, 18
...CRT, 31...DMA transfer request table.
Claims (1)
チヤネルに空きが存在するかどうかを判別する空
きチヤネル存在有無判別手段と、 ＤＭＡ転送要求を登録するＤＭＡ転送要求登録
手段と、 前記空きチヤネル存在有無判別手段が空きチヤ
ネルの存在を判別したときＤＭＡ転送要求登録手
段に登録された要求に応じて空きチヤネルを割り
当てる空きチヤネル割当手段、 とを具備することを特徴とするＤＭＡチヤネル
制御装置。 (2) ダイレクト・メモリ・アクセスを行うため
のチヤネルに空きが存在するかどうかを判別する
空きチヤネル存在有無判別手段と、 ダイレクト・メモリ・アクセスを行う要求とし
てのＤＭＡ転送の要求があつたときに空きチヤネ
ル存在有無判別手段が空きチヤネルの存在を判別
した場合、この空きチヤネルをＤＭＡ転送の要求
に対して割り当てる空きチヤネル割当手段と、 前記ＤＭＡ転送の要求があつたときに空きチヤ
ネル存在有無判別手段が空きチヤネルの不存在を
判別したときこのＤＭＡ転送要求を登録するＤＭ
Ａ転送要求登録手段と、 前記空きチヤネル存在有無判別手段が空きチヤ
ネルの存在を判別したときＤＭＡ転送要求登録手
段に登録された要求に応じて空きチヤネルを割り
当てる空きチヤネル割当手段、 とを具備することを特徴とするＤＭＡチヤネル
制御装置。[Scope of utility model registration claims] (1) DMA for direct memory access
an empty channel existence determining means for determining whether a channel is empty; a DMA transfer request registration means for registering a DMA transfer request; and a DMA transfer when the empty channel existence determining means determines the existence of an empty channel. A DMA channel control device comprising: empty channel allocation means for allocating an empty channel according to a request registered in a request registration means. (2) means for determining whether there is an empty channel for direct memory access; When the free channel presence/absence determining means determines the presence of a free channel, a free channel allocating means allocates the free channel in response to a DMA transfer request; and a free channel determining means for determining the presence/absence of a free channel when the DMA transfer request is received. When the DM determines that there is no free channel, the DM registers this DMA transfer request.
A transfer request registration means; and free channel allocation means for allocating an empty channel in accordance with a request registered in the DMA transfer request registration means when the free channel presence/absence determining means determines the existence of an empty channel. A DMA channel control device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6907889U JPH039045U (en) | 1989-06-15 | 1989-06-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6907889U JPH039045U (en) | 1989-06-15 | 1989-06-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH039045U true JPH039045U (en) | 1991-01-29 |
Family
ID=31604071
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6907889U Pending JPH039045U (en) | 1989-06-15 | 1989-06-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH039045U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007249635A (en) * | 2006-03-16 | 2007-09-27 | Nec Corp | Data transfer unit and data transfer method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6229831A (en) * | 1985-07-31 | 1987-02-07 | Yamatake Honeywell Co Ltd | One-action igniting device |
-
1989
- 1989-06-15 JP JP6907889U patent/JPH039045U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6229831A (en) * | 1985-07-31 | 1987-02-07 | Yamatake Honeywell Co Ltd | One-action igniting device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007249635A (en) * | 2006-03-16 | 2007-09-27 | Nec Corp | Data transfer unit and data transfer method |
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