JPH0393949U - - Google Patents

Info

Publication number
JPH0393949U
JPH0393949U JP83890U JP83890U JPH0393949U JP H0393949 U JPH0393949 U JP H0393949U JP 83890 U JP83890 U JP 83890U JP 83890 U JP83890 U JP 83890U JP H0393949 U JPH0393949 U JP H0393949U
Authority
JP
Japan
Prior art keywords
memory
cpu
detection circuit
invalid address
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP83890U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP83890U priority Critical patent/JPH0393949U/ja
Publication of JPH0393949U publication Critical patent/JPH0393949U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Storage Device Security (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
JP83890U 1990-01-09 1990-01-09 Pending JPH0393949U (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP83890U JPH0393949U (fr) 1990-01-09 1990-01-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP83890U JPH0393949U (fr) 1990-01-09 1990-01-09

Publications (1)

Publication Number Publication Date
JPH0393949U true JPH0393949U (fr) 1991-09-25

Family

ID=31504775

Family Applications (1)

Application Number Title Priority Date Filing Date
JP83890U Pending JPH0393949U (fr) 1990-01-09 1990-01-09

Country Status (1)

Country Link
JP (1) JPH0393949U (fr)

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