JPH0396290A - Manufacturing method for semiconductor laser - Google Patents

Abstract

PURPOSE:To facilitate the manufacture of a high quality and high performance semiconductor laser by using a mask layer for impurity diffusion, then side- etching a lower side mask layer, and turning the layer into a mask for forming a higher resistance layer. CONSTITUTION:After an SiO2 film 7 and an Si3N4 film 8 are formed on the upper surface of an n type GaAs contact layer 6, resist is spread on the surface, and aeolotropic etching is carried out so that an SiO2 stripe 71, and Si3N4 stripe 81 may be formed. They are used as a diffusion mask to diffuse Zn. An activity layer 4 for the Zn diffusion region is used as a mixed crystal layer 41 while an n type clad layer is used as a p type clad layer 51 and a p type contact layer 61. Then the Si3N4 stripe 81 is masked, and side-etched so that the surface of the p type contact layer 61 which is the Zn diffusion region, may be completely exposed. After the Si3N4 stripe 81 is removed in succession, the SiO2 strip 71 is masked where ion is injected, thereby forming a high resistant layer 63.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor laser having a buried multiple quantum well structure. Semiconductor lasers are used in a wide range of applications, such as light sources for optical communications and light sources for reading and writing compact discs or video discs.

[Prior art] In order to efficiently generate laser oscillation with as small an input current as possible, a current confinement structure or an optical waveguide structure is formed inside to concentrate the input current in the active layer and to narrow the generated light. It is effective to confine it to an area.

A buried multiple quantum well type semiconductor laser shown in FIG. 4 is known as having such a structure. In the figure, on a p-type GaAs substrate 1, a p-type GaAs buffer layer 2, a p-type ANGaAs first cladding layer 3, a multi-quantum well active N4, an n-type ANGaAs second cladding layer 5,
, n-type GaAs contact layers 6 are laminated. In the figure, Zn is diffused in the shaded area, and the second cladding layer 5 of the Zn diffusion region and the contact N6 are inverted to be p-type.
cladding layer 52 and a p-type contact layer 61, and the active layer 4 is mixed crystal to form a p-type Aj GaAs mixed crystal layer 4.
It is written as l. Further, an Si02 insulating film 7 is formed on the upper surface of the p-type contact layer 61.

In the above structure, when an n-type electrode 91 and a p-type electrode 92 are formed on the upper and lower surfaces, respectively, and a voltage is applied, the current is narrowed to the non-diffusion region sandwiched between the Zn diffusion regions and concentrated in the active layer 4. Further, the generated light is confined within the active layer 4 by the mixed crystal layer 41 and the upper and lower cladding layers 3 and 5.

[Problems to be Solved by the Invention] Incidentally, in the semiconductor laser having the above structure, in order to allow current to flow only in the non-diffusion region, the Si02 insulating film 7 is formed on the upper surface of the p-type contact layer 61. It is necessary to insulate between the n-type electrode 91 and the p-type contact layer 61. For this reason, conventionally, as shown in FIG. 5 (1), Z
After performing n diffusion, Si0 is deposited on the contact layers 6 and 6l.
2 insulating film 7 is formed over one surface, an etching mask 72 is further formed above the Zn diffusion region, and the SiO2 film 7 is etched.
The surface 62 of is exposed (Fig. 5 (2)).

However, since the width of the non-diffusion region is usually extremely small, 2 to 5 μm, it is difficult to match the mask when exposing the surface 62, and there is a risk that mask defects may occur and product yields may decrease.

The present invention attempts to solve such problems,
The purpose is to eliminate the difficulty of mask alignment and manufacture a high-performance buried multiple quantum well type semiconductor laser using a simple process.

[Means for Solving the Problems] In order to solve the above problems, in the present invention, a first cladding layer of a first conductivity type, a multi-quantum well active layer, a second conductivity type are formed on a semiconductor substrate of a first conductivity type. After sequentially laminating second cladding layers of a shape, forming a contact layer made of a semiconductor of a second conductivity type on the top surface thereof, and forming a mask layer made of two layers having different etching characteristics at a predetermined location on the top surface of the contact layer. using this as a mask to diffuse impurities from the contact layer to make the active layer in the impurity diffusion region a mixed crystal; and using the upper mask layer as an etching mask, A process of side etching the mask layer to completely expose the surface of the contact layer in the impurity diffusion region, and implanting ions into the exposed surface using the lower mask layer as a mask, forming a high resistance layer on the surface of the contact layer in the impurity diffusion region. A semiconductor laser is manufactured by a process of forming a semiconductor laser.

[Operation] In the above method, after the mask layer is used as a mask for impurity diffusion, side etching of the lower mask layer is performed to further use it as a mask for forming a high resistance layer. In other words, when impurities are diffused, the impurities penetrate to the bottom of the mask layer to some extent, but by taking advantage of the difference in etching characteristics between the upper and lower mask layers and greatly etching only the sides of the lower mask layer, the impurity diffusion area can be etched. It is possible to completely expose the surface of the Also, at this time, the upper mask layer acts as a surface protective layer for the lower mask layer.

Thereafter, by implanting ions using the lower mask layer as a mask, a high resistance layer that reliably covers the surface of the impurity diffusion region is formed. Since the high-resistivity layer acts as an insulating layer, current is not introduced into the impurity diffusion region, but is narrowed to the non-diffusion region and concentrated in the active layer. [Example] FIGS. 1 (1) to (5) are cross-sectional views sequentially showing the steps of manufacturing a semiconductor laser having a buried multiple quantum well structure by the manufacturing method of the present invention.

Hereinafter, the manufacturing method of the present invention will be explained in detail based on the drawings.

First, in the step shown in FIG. 1 (1), a film is deposited on a p-type GaAs substrate l by a known method such as the molecular beam crystallization method (CMBE method) or the metal organic chemical vapor deposition method (MOCVD method).
p-type GaAs buffer layer 2, p-type An xGa1-xA
s cladding layer 3, multiple quantum well (MQW>active M4, n
A type A1xGa1-xAs cladding layer 5 and an n-type GaAs contact layer 6 are sequentially laminated.

The active layer 4 has 11! a yGat-yAs barrier layer,
GaAs or AlzGat-zAs well layers are alternately stacked. At this time, the A1 mixed crystal ratios y, z and the thicknesses of the barrier layer and the well layer are determined as appropriate based on the desired oscillation wavelength. As an example, when the desired oscillation wavelength is 865 nm, the barrier layer thickness may be 3.5 nm when y=0.15, and the well layer thickness may be 12 nm when z=0.

Further, on the upper surface of the n-type GaAs contact layer 6, a thermal CV
By D method, plasma CVD method, sputtering method, etc.
For example, the SiO2 film 7 is made of Si3N4 to a thickness of 0.5 μm.
The films 8 are sequentially formed to a thickness of, for example, 0.1 μm. SiO
The thickness of the second film 7 only needs to be thick enough to serve as a mask during Zn diffusion and Ar implantation in the subsequent process, and in this embodiment, the thickness is 0.000. Although the thickness is 5 μm, it is not limited to this, and may be changed as appropriate depending on the diffusion or implantation conditions. In addition, the thickness of the SiaN4 film 8 will be determined by
It is sufficient if the thickness is sufficient to serve as a mask when side etching the O2 film 7, and the thickness can be selected as appropriate.
Considering that cracks are likely to occur when the thickness of N4 is 0.1 μm or more, the thickness was set to 0.1 μm in this example.

After forming each layer in this way, a resist (not shown) is applied to the upper surface, and a photolithography process and a dry etching process are performed to form the SiO2 film 7 and the SiO2 film 7.
The 3N4 film 8 was anisotropically etched to form SiO2 stripes 71 and Si3N4 stripes 81 as shown in FIG.
The SisN4 stripes 81 constitute a mask layer during impurity diffusion.

Here, as the etching gas, for example, CF4 can be used, and in this case, S. i3Na, Si02, G
The ratio of etching rates for each layer of aAs is
If 4 is 1, SiO2 is about 1/3 and GaAS is about 1/100, so the etching is n-type GaA.
The process stops almost automatically when the s-contact layer 6 appears.

Next, using the SiO2 stripes 71 and the Si3N4 stripes 8l as diffusion masks, Zn, which is a p-type impurity, is diffused from the n-type GaAs contact layer 6 to the p-type A.
f! A Zn diffusion region 10 (indicated by diagonal lines in the figure) is formed over the xGa1-xAs cladding layer 3.The Zn diffusion concentration is the concentration at which the active layer 4 is destroyed and becomes a mixed crystal, that is, usually 1 x 1018d or more. , here it is set to 3 X 1 0i8tffl to ensure mixed crystallization.Z
The n-diffusion region 10 spreads downward and also spreads isotropically in the lateral direction, and penetrates to some extent below the SiOz stripe 71 and the S13N4 stripe 8l. Therefore, when forming the stripes 71 and 81, it is necessary to make the width larger than the desired emission width (width of the non-diffused region) by the amount of Zn intrusion.

Zn diffusion methods include the sealed tube method, in which the Zn source, As source, and sample are sealed in a closed tube and heated and diffused, or a GaAs solution in which a predetermined amount of Zn is dissolved is used as the diffusion source, and a board with small holes is used. Although it is possible to use a semi-seal diffusion method using a solution source in which diffusion is carried out by contacting the solution for a predetermined period of time through be. Also, this allows Zn
The active layer 4 in the diffusion region is converted into a mixed crystal layer 41, and the n-type cladding layer 5 and n-type contact layer 6 are inverted to be p-type and converted into a p-type cladding layer 51. This becomes a p-type contact layer 61.

After Zn diffusion, as shown in Figure 1 (3), Si3N4
Using stripe 81 as a mask, Si02 stripe 7
Side etching is performed until the width of layer 1 becomes smaller than the width of n-type GaAs contact layer 6 which has not undergone Zn diffusion. As an etching solution, for example, HF/NH4 F=1/
23 sets can be suitably used, in which case SiO2
The etching rate is about 0.5μm/10min,
Since Si3Na and GaAs are hardly attacked,
It becomes possible to etch only the side surface of the SiO2 stripe 7l. Also, this Si02 stripe 7l
Since side etching proceeds isotropically from both sides of the stripe, controlling the etching time ensures that the width of the SiO2 stripe 71 after etching is smaller than the width of the n-type contact layer 6 in the non-diffused region. In other words, the p-type contact layer 6, which is a Zn diffusion region,
It is possible to completely expose the surface of the

After the side etching is completed, the Si3N4 stripes 81 are subsequently removed. As a removal method, hot phosphoric acid (l
A method of selectively removing Si3N4 at a temperature of about 80°C, SL3N4 in the dry etching using CFa described above.
A method that utilizes the difference in etching speed between SiOz and SiOz can be adopted.

After that, in FIG. 1 (4), the SiOz stripe 7
1 as a mask, Ar is ion-implanted shallowly at a low acceleration voltage to form a high resistance layer 63 that completely covers the surface of the p-type contact layer 6.

Here, FIG. 2 shows the results of calculations based on the LSS theory regarding the acceleration voltage, implantation density, and implantation depth when the Ar dose is IX1011Ci1 and the implanted material is GaAs. Furthermore, according to experiments conducted by the present inventors, defects are generated in the ion implantation region due to the impact of ion implantation, and the depth of the defects reaches approximately three times the ion implantation depth shown in FIG. It is clear that Therefore, it is important to consider this defect depth when implanting ions, for example 3
If implanted at 0 kV, the defect depth will be approximately 150 nm, but since the design thickness of the contact layer 6 is approximately 500 nm, the effect will be limited to the surface layer of the p-type contact layer 61, and the light emitting characteristics will be affected. The cladding layer 5 has a big influence on
will never reach.

Regarding the implantation of high-resistance ions, a method is known in which light elements such as H+ (protons) and He are implanted at a high acceleration voltage of 100 kV or more. However, with this method, the implantation depth is 1 μm or more. It is estimated that the depth of the induced defect becomes even deeper.In such a state, the defect injected from between the SiO2 stripe 71 and the Zn diffusion region 10 penetrates the contact layer 6 and reaches the cladding layer 5.
, and may even reach active J'I4.

If defects are implanted into these layers, which are important regions for light emission, there is a risk of deteriorating luminous efficiency, lifetime, etc. Therefore, heavy elements such as Ar in this example are used as implanted ions, and low It is desirable to implant defects at an accelerating voltage to reduce the depth of defect introduction.

The dose required to increase the resistance is determined by the impurity concentration of the n-type GaAs contact layer 6 and the Zn diffusion concentration. For example, the impurity concentration of the n-type contact layer 6 is 2X101Baf.
Zn diffusion concentration, which is a p-type impurity, is 3 x 1 0i8f
, then p of the difference l×103BOl1
It is necessary to crush the shaped carrier by ion implantation. Ar
The increase in resistance due to ion implantation (implantation of inert atoms) is mainly due to the capture of carriers by induced defects. Therefore, in order to crush the p-type carriers of I However, it is difficult to accurately estimate the required ion implantation amount, so currently the dose is determined experimentally.

After the ion implantation, as shown in FIG. 1(5), the Si02 stripe 71 is removed using a hydrofluoric acid etching solution, and an n-type electrode 9l is formed on its upper surface to complete the product.

In this way, according to the above method, the photolithography process is performed using a mask M (SiO2 stripe 71) for impurity diffusion.
, Si3Na stripes 81>, and does not require sophisticated mask alignment techniques. Moreover, ion implantation can be performed using this impurity diffusion mask layer, and the Zn diffusion region can be reliably insulated with a simple process.

Next, a second embodiment of the present invention will be described with reference to FIG. FIGS. 3(2) and (5) correspond to the steps in FIGS. 1(2) and (5) in the first embodiment, respectively, and the element shown in FIG. 1 is rotated 90" and viewed from the side. This corresponds to a cross-sectional view taken in the direction of the resonator.

The first embodiment above is an example of a semiconductor laser with a normal output (up to about 10 mW), and the current is narrowed only in the width direction of the stripe, and the current is particularly narrowed in the length direction of the stripe and in the cavity direction. In this example, in addition to the element structure of the first example, Zn was diffused on both end faces in the direction of the resonator in order to increase the output of the semiconductor laser. The region 10 is formed to narrow the current, and the manufacturing method of the present invention can also be applied to this case.

When manufacturing the semiconductor laser of this example, the basic steps are the same as those of the first example. First, each layer is formed in the same manner as in the first example, and then },
By etching SiO2 stripe 71, SiaNa
Stripes 81 are formed.

At this time, as shown in FIG. 3(2), each stripe 71
, 81 in the longitudinal direction are simultaneously removed, and then Zn is diffused using each stripe 71, 8 as a mask, thereby forming Zn diffusion regions 10 on both end faces in the longitudinal direction.

Furthermore, side etching of the SiO2 stripe 71 is performed in the same manner as in the first embodiment (process diagram omitted).
The width and length of the O2 stripe 72 are adjusted so that they are both smaller than the width and length of the contact layer 6 in the non-diffusion region, so that the surface of the Zn diffusion region 10 is completely exposed.

Next, in FIG. 3 (5), Ar ions are implanted to form a high resistance layer 63 on the surface of the p-type contact layer 6l. As a result, in the same process as in the first embodiment,
Current narrowing in the resonator direction can be achieved at the same time.

In general, the factors that cause element destruction when increasing the optical output are:
A large proportion of COD damage occurs when the temperature of the end face rises rapidly due to light absorption at the output end face, leading to melting. In order to prevent this, it is effective to make the energy gap at the output end face larger than the inside, thereby making the end face transparent to the emission wavelength and reducing light absorption. In this example, a mixed crystal region I of a multiple quantum well formed by Zn diffusion is formed on the output end face.
This is achieved by forming O. Also, Ar
The high resistance layer 63 formed by ion implantation prevents current from flowing into the Zn diffusion region 10 on the emission end face, and prevents a temperature rise due to Joule heat at the end face. In this way, by employing the method of the present invention, a higher output semiconductor laser can be easily realized.

[Effects of the Invention] As described above, according to the manufacturing method of the present invention, there is no need for mask alignment that requires advanced technology, so there is no risk of defective elements occurring due to mask defects, and high quality can be easily achieved. Moreover, a high-performance semiconductor laser can be manufactured.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the manufacturing process of a semiconductor laser according to the first embodiment of the present invention, FIG. 2 is a diagram showing the relationship between implantation depth and implantation density of Ar ions, and FIG. 3 is a diagram showing the relationship between implantation depth and implantation density of Ar ions, and FIG. 3 is a diagram showing the manufacturing process of a semiconductor laser according to the first embodiment of the invention. FIG. 4 is an overall sectional view of a conventional semiconductor laser, and FIG. 5 is a manufacturing process diagram of a conventional semiconductor laser. 1...p-type GaAs substrate (semiconductor substrate) 3-=
-P-type AN xGa1-xAs cladding N (first cladding layer) 4...Multi-quantum well active layer 41...Mixed crystal layer 5...N-type AJ! xGa1-xAs cladding layer (second cladding layer) 6...n-type GaAs contact layer 61...
...p-type GaAs contact layer 63 ...high resistance layer 71 ...SiO2 stripe (mask layer) 81
・・・・・・Si3N4 stripe (mask layer>10・
...Impurity diffusion region Fig. 1 Fig. 1

Claims (1)

[Claims] After sequentially stacking a first cladding layer of the first conductivity type, a multi-quantum well active layer, and a second cladding layer of the second conductivity type on a semiconductor substrate of the first conductivity type, A step of forming a contact layer made of a semiconductor of a second conductivity type, and forming a mask layer consisting of two layers with different etching characteristics at a predetermined location on the upper surface of the contact layer, and using this as a mask to diffuse impurities from the contact layer. The active layer in the impurity diffusion region is mixed crystal, and the upper mask layer is used as an etching mask to side-etch the lower mask layer to completely cover the surface of the contact layer in the impurity diffusion region. A method for manufacturing a semiconductor laser, comprising the steps of: exposing the contact layer to the exposed surface using a lower mask layer as a mask; and implanting ions into the exposed surface using a lower mask layer as a mask to form a high resistance layer on the surface of the contact layer in the impurity diffusion region. .