JPH04101538A - Cpu output data control circuit - Google Patents

Abstract

PURPOSE:To reduce a circuit scale and simplify transfer control considerably by controlling the CPU so that when one memory is in a write mode, the other memory is in a read mode to prevent the occurrence of lacing. CONSTITUTION:In a period of time when CPU 1 keeps a switch signal W/R at high level, a selector 3 connects a RAM 5 to the address bus of the CPU, and a selector 4 connects a RAM 6 to the address bus of an address counter. On the other hand since the RAM 5 is in a write mode, it reads, in accordance with an output address signal of address counter 2, CPU data that was written in the RAM 5 precedently and sends the CPU data read out to the data bus of CPU. Since a selector 7 selects the data bus at the side of RAM 6, the read out CPU data is sent out to the multiplexer apparatus via a parallel/serial converter 8.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a CPU output data control circuit, and in particular to a CPU output data control circuit.
The present invention relates to a CPU output data control circuit that prevents the danger of racing that occurs when multiplexing output data of a CPU.

(Prior art) For example, in a time division multiplex communication device, a multiplexer forms a transmission frame by time-divisionally arranging a plurality of multiplexed CPU output data, but the CPU output data is not used for lift processing. Since the data is output at a constant speed, the speed is usually slower than the speed at which the multiplexer takes in the data to be multiplexed, and the output timing may not be performed at regular intervals. Therefore, simply providing a RAM between the CPU and the multiplexer may cause racing as shown in FIG. That is, for example, the fourth
When the CPU output data multiplexed into the th time slot TS4 is 4 words (wl~W4), the 4 words (wl~W,) of the CPU output data are written to the RAM, but this is a software process. , as shown in FIG. 3(b), the writing timing of word w3 may be delayed than usual, and each word may not be written at regular time intervals. Then, since the timing at which the multiplexer reads from the RAM is a fixed time interval defined by the hardware, as shown in FIG. 3(a), the word W! Words W3 and W2 are read after the CPU output data is written, but words W3 and W4 are read before the CPU output data is written. That is, the multiplexer reads the previous CPtJ output data as words W3 and W4. As a result, in the data multiplexed in the time slot TS4 of the frame, the words wl and W2 are new data, and the words W3 and W4 are old data, as shown in FIG. 3(c).

In this way, while the CPLI is writing to RAM, the reading from the multiplexer side overtakes and overtakes it, causing the read data to be mixed with old and new data.This phenomenon is called racing.To prevent this, conventional methods have been used, for example, as shown in CP as shown
Equipped with a U output data control circuit. This CPU output data control circuit has an F I F between the CPU 21 and the RAM 24.
O (First InFirst 0ut) 22 and controller 23 are arranged, and the CPU output data for one time slot (four words in Fig. 3) is sent to the CPU 2.
The controller 23 writes the contents of the FIFO 22 to the FIFO 22 at the timing of
Write to AM24, then controller 23 writes to RAM
The contents of 24 are read out and output to a multiplexing device (not shown) via a parallel-to-serial converter 25 to prevent racing from occurring.

Here, transfer control is performed as follows.

The controller 23 is provided with registers that store control information and status regarding the FIF 22 and the RAM 24, and control over whether or not to write to the FIFO 22 and read control are performed based on the contents of these registers. C
When PU21 finishes writing to FIFO22, C
The PU 21 sets an end flag in the register. The controller 23 checks the end flag and the output control signal of the FIFO 22, reads the data from the F○F○22, and
Transfer to AM24. At this time, it is determined whether the transfer was successful or not, and a flag indicating the result is set in the register i. If all transfers are successful, then R
A reading operation is performed from the AM 24. On the other hand, if the transfer fails, the flag to that effect is read by the CPU 21 (
(not shown) functions as a retransmission request, and writing to the FIFO 22 is restarted.

(Problems to be Solved by the Invention) In the conventional CPU output data control circuit described above, in order to ensure reliability of transfer control, the functions required of the controller are enormous and complicated control is required. Furthermore, the circuit scale also increases. Therefore, if the system is constructed from individual parts, the probability of failure will increase and the reliability of the entire system will be significantly impaired, so LSI implementation is essential. That is, the number of design steps required for LSI integration increases, and the design cost increases.

The present invention has been made in view of these concerns, and its purpose is to reliably control the transfer of CPU output data to a multiplexing device without causing racing with a simple configuration that does not require LSI integration. The object of the present invention is to provide a CPU output data control circuit that obtains the following results.

(Means for Solving the Problems) In order to achieve the above object, the CPU output data control circuit of the present invention has the following configuration.

That is, the CPU output data control circuit of the present invention is a CPU output data control circuit that controls the transfer timing when data output from the CPU is transferred to the multiplexing device; These are two memories connected to each of the two branched data buses, one of which receives the switching signal output from the CPU in a write mode to take in data on the data bus, and the other to output data to the multiplexing device. first and second memories each set to a read mode; an address counter that generates an address signal for the memory in the read mode; and a CPU.
and the address signal output from the address counter are respectively input to the selectors, one of which selects and outputs one of the two input address signals to the first memory in response to the switching signal, and the other selects and outputs one of the two input address signals to the first memory. outputs the other of the two input address signals to the second memory.
and a second selector; upon receiving the switching signal, the second selector
The third selector selectively outputs the output data of the memory in the read mode among the two memories.

(Function) Next, the function of the CPU output data control circuit of the present invention configured as described above will be explained.

In the present invention, two memories to which the CPU can directly write are provided, and when one memory is in the write mode, the other memory is controlled by the CPU to be in the read mode, thereby preventing racing from occurring.

In this way, compared to conventional circuits, it is possible to significantly reduce the circuit scale and simplify transfer control, eliminating the need for LSI, and making it possible to significantly reduce the number of design steps.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a CPU output data control circuit according to an embodiment of the present invention. In FIG. 1, the data bus of the CPUI is branched into two branches, a RAM 5 is connected to one branch data bus, and a RAM 6 is connected to the other branch data bus. This two-branch data bus is connected to the input end of the selector 7 on the downstream side of the RAM (5, 6). The other branch address bus is connected to the other input end of the selector 4. Similarly, the address bus of the address counter 2 is branched into two, one branch address bus being connected to the other input end of the selector 3, and the other branch address bus being connected to one input end of the selector 4.

The CPU 1 then sends the switching signal W/ by software processing.
It is designed to output R. The switching signal W/R is a level signal consisting of either a high level (W) or a low level (R>), and its level is inverted every time the CPU completes outputting CPU data for one time slot.This switching signal W/R41' is directly applied to the SEL terminal of selector 3 and 7 and the WE terminal of RAM5, and is also applied to selector 4.
is applied to the SEL terminal of RA via the inverter 9.
A voltage is applied to the WE terminal of M6 via the inverter 10.

Selectors 3 and 4 select the address bus (C) connected to one input terminal when the signal level of the SEL terminal is high.
On the other hand, when the level is low, the address bus connected to the other input terminal (the address bus of address counter 2) is selected. The output address signal of selector 3 is applied to RAM5, and the output address signal of selector 4 is applied to RAM6.

The RAMs 5 and 6 are in write mode when the signal level of the WE terminal is high, and are in read mode when it is low.

The selector 7 selects the data bus on the RAM 6 side when the signal level of the SEL terminal is high, and conversely selects the data bus on the RAM 5 side when the signal level is low. in short,
The selector 7 selects the RAM in read mode and outputs its output data to the parallel-to-serial converter 8.

In the above configuration, during the period in which the CPU 1 sets the switching signal W/R to a high level, the selector 3 connects the RAM 5 to the address bus of the CPU, and the selector 4 connects the RAM 6 to the address bus of the address counter. RAM5
Since it is in write mode, it takes in the CPU data on the data bus.

On the other hand, although RAM 6 is in read mode, the CPU data written last time is sent to the read data bus according to the output address signal of address counter 2. Since selector 7 selects the data bus on the RAM 6 side, the CPU data written last time is sent to the read data bus. The CPU data is sent via a parallel to serial converter 8 to a multiplexer.

It is possible to prevent racing by simple switching control without requiring complicated control as in the past.

(Effects of the Invention) As explained above, according to the CPU output data control circuit of the present invention, two memories to which the CPU can directly write are provided, and when one memory is in the write mode, the other memory is in the write mode. The CPU controls the memory to be in read mode,
Since the occurrence of racing is prevented, the circuit size can be significantly reduced and transfer control simplified compared to conventional circuits, eliminating the need for LSI, and significantly reducing design man-hours. There is.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram of a CPU output data control circuit according to an embodiment of the present invention, FIG. 2 is a configuration block diagram of a conventional CPU output data control circuit, and FIG. 3 is a diagram showing an example of racing. . 1...CPtJ, 2...Address counter, 347...Selector, 5.6...
...RAM, 8...Parallel-serial converter.

Claims (1)

[Claims] A CPU output data control circuit that controls the transfer timing when data output from the CPU is transferred to a multiplexing device; this CPU output data control circuit is connected to each of two branched data buses of the CPU. two memories, one of which is set in a write mode to take in data on a data bus in response to a switching signal output from the CPU, and the other to a read mode to output data to a multiplexer. 2; an address counter that generates an address signal for the memory in read mode; and a CPU.
and the address signal output from the address counter are respectively input to the selectors, one of which selects and outputs one of the two input address signals to the first memory in response to the switching signal, and the other selects and outputs one of the two input address signals to the first memory. outputs the other of the two input address signals to the second memory.
and a second selector; and a third selector that receives the switching signal and selects and outputs the output data of the memory in the read mode among the two memories.