JPH04105405A - Delay circuit - Google Patents
Delay circuitInfo
- Publication number
- JPH04105405A JPH04105405A JP22391590A JP22391590A JPH04105405A JP H04105405 A JPH04105405 A JP H04105405A JP 22391590 A JP22391590 A JP 22391590A JP 22391590 A JP22391590 A JP 22391590A JP H04105405 A JPH04105405 A JP H04105405A
- Authority
- JP
- Japan
- Prior art keywords
- transmission line
- printed circuit
- terminals
- delay circuit
- delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims abstract description 25
- 230000001934 delay Effects 0.000 claims description 3
- 239000004020 conductor Substances 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000010030 laminating Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 229910000859 α-Fe Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000696 magnetic material Substances 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
Landscapes
- Waveguide Switches, Polarizers, And Phase Shifters (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、波形の時間調整、パルスの生成、線型量の補
償などの目的で使用される分布定数型遅延回路に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a distributed constant delay circuit used for purposes such as waveform time adjustment, pulse generation, and linear quantity compensation.
本発明は、分布定数型の遅延回路において、マイクロス
トリップ形状の伝送線路が形成されたプリント基板を積
層して構成することにより、製造工程の簡略化を図るこ
とができるようにしたものである。The present invention is a distributed constant type delay circuit that is configured by laminating printed circuit boards on which microstrip-shaped transmission lines are formed, thereby simplifying the manufacturing process.
従来の分布定数型遅延回路の構造を第７図に示す。フェ
ライト１２などの磁性材料の表面に内部導体１３をコイ
ル状に巻いてインダクタンスを増加させ、さらに内部導
体１３と外部導体１０の間に誘電体１１を配したもので
ある。FIG. 7 shows the structure of a conventional distributed constant type delay circuit. An internal conductor 13 is coiled around the surface of a magnetic material such as ferrite 12 to increase inductance, and a dielectric 11 is further arranged between the internal conductor 13 and the external conductor 10.
このような従来の分布定数型遅延回路は、一般にインダ
クタンスＬの方が静電容量Ｃよりも大きくなるので、こ
の回路の持つ特性インピーダンスｚｏ＝Ｖ’Ｔ７てか高
くなり、その結果として、端末に存在する浮遊容量の影
響を受けやすく、遅延時間の長い遅延回路はど遅延可能
な信号周波数は低くなり、高周波信号の遅延ができなく
なる問題がある。また、フェライトの上にコイルを巻き
、さらにその上に誘電体を被せる構造のために、製造工
程が複雑になる問題がある。そしてこのような構造のた
めに、遅延時間を可変させることが困難である問題があ
る。In such a conventional distributed constant delay circuit, the inductance L is generally larger than the capacitance C, so the characteristic impedance of this circuit, zo=V'T7, becomes quite high, and as a result, the terminal A delay circuit that is easily affected by the existing stray capacitance and has a long delay time has the problem that the signal frequency that can be delayed becomes low, making it impossible to delay high-frequency signals. In addition, the structure involves winding a coil on top of the ferrite and then covering it with a dielectric, which makes the manufacturing process complicated. Due to this structure, there is a problem in that it is difficult to vary the delay time.
本発明は、このような問題点を解決するもので、高周波
信号の遅延が可能であり、製造工程の簡略化および遅延
時間の可変化を図ることのできる遅延回路を提供するこ
とを目的とする。The present invention solves these problems, and aims to provide a delay circuit that can delay high-frequency signals, simplify the manufacturing process, and make the delay time variable. .
本発明は、信号が与えられる一つの端子と、この信号に
遅延を与える分布定数回路と、この分布定数回路を経由
する信号が与えられる別の端子とを備えた遅延回路にお
いて、マイクロストリップ形状の伝送線路が分布定数回
路として形成され、この伝送線路の両端のそれぞれに電
気的に接続された導電路をなすスルーホールをもち、そ
の複数枚が積層されるプリント基板を備えたことを特徴
とする。The present invention provides a microstrip-shaped delay circuit that includes one terminal to which a signal is applied, a distributed constant circuit that delays this signal, and another terminal to which a signal passing through this distributed constant circuit is applied. The transmission line is formed as a distributed constant circuit, and the transmission line has a through hole forming a conductive path electrically connected to each end of the transmission line, and a printed circuit board is provided in which a plurality of the through holes are laminated. .
ここで、上記端子の一方にかかわるスルーポールは、上
記プリント基板ごとに異なる位置に設けられ、このスル
ーホールを上記端子の一方に電気的に切り換え接続する
切換手段を備えることが望まれる。Here, it is desirable that the through-pole related to one of the terminals be provided at a different position for each of the printed circuit boards, and that a switching means be provided for electrically switching and connecting the through-hole to one of the terminals.
プリント基板上に形成し伝送線路の特性インピーダンス
は、線路幅およびグランドまでの間隔で定まる。これに
より、高周波信号の遅延を実現する。また、切換器で回
路長を変化させて遅延時間を可変設定することができる
。The characteristic impedance of a transmission line formed on a printed circuit board is determined by the line width and the distance to ground. This realizes delay of high frequency signals. Furthermore, the delay time can be variably set by changing the circuit length using a switch.
以下、本発明の一実施例を図面を参照して説明する。第
１図から第６図は、この実施例の構造を示す図である。Hereinafter, one embodiment of the present invention will be described with reference to the drawings. 1 to 6 are diagrams showing the structure of this embodiment.
第１図は１層目および２層目となるプリント基板の表側
であり、第２図はこのプリント基板の裏側である。１お
よび２は各プリント基板の伝送線路端子である。伝送線
路端子１および２は、各々スルーホールである。３はプ
リント基板間グランド接続用スルーホールである。４は
切替器出力端子である。５はインダクタンス成分となる
伝送線路をマイクロストリップの形状で作成したもので
ある。第３図は第１図のＡ−Ａ’の断面図であり、６は
第１図に示した面であり、７は第２図に示した面である
。８は各面の間を絶縁するために用いる絶縁体（誘電体
）である。第４図は３層目および４層目となるプリント
基板の表側であり、裏側は第２図と同じくなる。このよ
うな各プリント基板を第５図に示すように多層化し、各
プリント基板のスルーホールを接続する。FIG. 1 shows the front side of the first and second layer printed circuit boards, and FIG. 2 shows the back side of the printed circuit boards. 1 and 2 are transmission line terminals of each printed circuit board. Transmission line terminals 1 and 2 are each through holes. 3 is a through hole for ground connection between printed circuit boards. 4 is a switch output terminal. Reference numeral 5 shows a transmission line serving as an inductance component made in the shape of a microstrip. FIG. 3 is a cross-sectional view taken along line AA' in FIG. 1, where 6 is the plane shown in FIG. 1 and 7 is the plane shown in FIG. 2. 8 is an insulator (dielectric material) used to insulate between each surface. FIG. 4 shows the front side of the third and fourth layer printed circuit boards, and the back side is the same as FIG. 2. Each of these printed circuit boards is multilayered as shown in FIG. 5, and the through holes of each printed circuit board are connected.
すなわち、この実施例は、信号が与えられる一つの端子
と、この信号に遅延を与える分布定数回路と、この分布
定数回路を経由する信号が与えられる別の端子とを備え
、さらに、本発明の特徴とする手段として、マイクロス
） ＩＪツブ形状の伝送線路５が分布定数回路として形
成され、この伝送線路５の両端のそれぞれに電気的に接
続された導電路をなすスルーホールである伝送線路端子
１および２をもち、その複数枚が積層されるプリント基
板と、上記端子の一方にかかわるスルーホールは、上記
プリント基板ごとに異なる位置に設けられ、このスルー
ホールを上記端子の一方に電気的に切り換え接続する切
換器９を備える。That is, this embodiment includes one terminal to which a signal is applied, a distributed constant circuit that delays this signal, and another terminal to which a signal passing through this distributed constant circuit is applied. As a characteristic means, an IJ tube-shaped transmission line 5 is formed as a distributed constant circuit, and transmission line terminals that are through holes forming conductive paths electrically connected to both ends of the transmission line 5 are provided. 1 and 2, in which a plurality of printed circuit boards are stacked, and a through hole related to one of the terminals is provided at a different position for each printed circuit board, and this through hole is electrically connected to one of the terminals. A switch 9 is provided for switching and connecting.
次に、この実施例の動作を説明する。第５図に示すよう
に、各プリント基板の伝送線路端子２を切替器９により
選択すると、遅延回路長を物理的に変化させることがで
きる。これにより、切替器出力端子４には遅延時間を変
化させた信号が出力される。Next, the operation of this embodiment will be explained. As shown in FIG. 5, when the transmission line terminal 2 of each printed circuit board is selected by the switch 9, the delay circuit length can be physically changed. As a result, a signal with a different delay time is output to the switch output terminal 4.
各プリント基板のグランドを同電位にするためにグラン
ド接続用スルーホール３を第６図のごとく縦方向にすべ
て接続する。In order to make the grounds of each printed circuit board the same potential, all the ground connection through holes 3 are connected in the vertical direction as shown in FIG.
遅延回路としてのインダクタンス成分はマイクロストＩ
Ｊツブの形状で実現し、またキャパシタンス成分は伝送
線路とグランド間の容量成分で実現している。各プリン
ト基板の伝送線路端子２を切替器９で選択すると、遅延
回路長が物理的に変化し、伝送線路のインダクタンスＬ
とキャパシタンスＣが変化して遅延時間１． ＝ゾＴで
が変わる。The inductance component as a delay circuit is Microst I
It is realized in the shape of a J-tube, and the capacitance component is realized as a capacitance component between the transmission line and the ground. When the transmission line terminal 2 of each printed circuit board is selected by the switch 9, the delay circuit length physically changes, and the inductance L of the transmission line changes.
, the capacitance C changes and the delay time 1. =ZoT changes.
本発明は、以上説明したように、プリント基板にマイク
ロストリップ形状の伝送線路を作成し、スルーホールを
介して各プリント基板が接続され、各プリント基板を接
層した構造を持つことにより伝送線路の特性インピーダ
ンスが線路幅およびグランドまでの間隔で決まるので、
多層化しても特性インピーダンスはほぼ一定となり、高
周波信号の遅延が可能となり、また製造工程の簡略化が
図れる効果がある。また、各プリント基板を接続してい
るスルーホールを選択する切替器を有しているので、遅
延回路長を物理的に変化させ遅延時間を可変する効果が
ある。As explained above, the present invention creates a microstrip-shaped transmission line on a printed circuit board, connects each printed circuit board through a through hole, and has a structure in which each printed circuit board is layered. Since the characteristic impedance is determined by the line width and the distance to ground,
Even when multi-layered, the characteristic impedance remains almost constant, making it possible to delay high-frequency signals and simplifying the manufacturing process. Furthermore, since it has a switch that selects the through hole connecting each printed circuit board, it has the effect of physically changing the delay circuit length and varying the delay time.
第１図は、本発明の１層目および２層目となるプリント
基板の表側の姿図。
第２図は第１図の裏側の姿図。
第３図は第１図のＡ−Ａ’断面図。
第４図は３層目および４層目となるプリント基板の表側
の姿図。
第５図は各プリント基板を多層化し、各プリント基板の
スルーホールを接続した断面図。
第６図は第５図の斜視図。
第７図は従来例の構造図。
１．２・・・伝送線路端子、３・・・グランド接続用ス
ルーホールへ４・・・切替器出力端子、５・・・伝送線
路、６・・・第１図側のパターン面、７・・・第２図側
のパターン面、８・・・絶縁体く誘電体）、９・・・切
替器、ｌＯ・・・外部導体、１１・・・誘電体、１２・
・・フェライト、１３・・・内部導体。FIG. 1 is a view of the front side of a printed circuit board serving as the first layer and second layer of the present invention. Figure 2 is a view of the back side of Figure 1. FIG. 3 is a sectional view taken along the line AA' in FIG. FIG. 4 is a view of the front side of the third and fourth layer printed circuit boards. FIG. 5 is a cross-sectional view showing how each printed circuit board is multilayered and the through holes of each printed circuit board are connected. FIG. 6 is a perspective view of FIG. 5. FIG. 7 is a structural diagram of a conventional example. 1.2...Transmission line terminal, 3...To through hole for ground connection 4...Switcher output terminal, 5...Transmission line, 6...Pattern surface on the side of Figure 1, 7. ...Pattern surface on the side of Figure 2, 8...Insulator/dielectric), 9...Switcher, lO...External conductor, 11...Dielectric, 12...
...Ferrite, 13...Internal conductor.
Claims (2)
与える分布定数回路と、この分布定数回路を経由する信
号が与えられる別の端子とを備えた遅延回路において、 マイクロストリップ形状の伝送線路が分布定数回路とし
て形成され、この伝送線路の両端のそれぞれに電気的に
接続された導電路をなすスルーホールをもち、その複数
枚が積層されるプリント基板 を備えたことを特徴とする遅延回路。1. In a delay circuit that has one terminal to which a signal is applied, a distributed constant circuit that delays this signal, and another terminal to which a signal passing through this distributed constant circuit is applied, a microstrip-shaped transmission line is distributed. A delay circuit formed as a constant circuit, having through holes forming conductive paths electrically connected to both ends of the transmission line, and comprising a printed circuit board on which a plurality of through holes are laminated.
リント基板ごとに異なる位置に設けられ、このスルーホ
ールを上記端子の一方に電気的に切り換え接続する切換
手段を備えた特許請求項１記載の遅延回路。2. 2. The delay circuit according to claim 1, wherein a through hole relating to one of the terminals is provided at a different position for each of the printed circuit boards, and further comprising switching means for electrically switching and connecting the through hole to one of the terminals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22391590A JPH04105405A (en) | 1990-08-24 | 1990-08-24 | Delay circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22391590A JPH04105405A (en) | 1990-08-24 | 1990-08-24 | Delay circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04105405A true JPH04105405A (en) | 1992-04-07 |
Family
ID=16805709
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22391590A Pending JPH04105405A (en) | 1990-08-24 | 1990-08-24 | Delay circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04105405A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007005951A (en) * | 2005-06-22 | 2007-01-11 | Hitachi Media Electoronics Co Ltd | Transmission circuit, antenna duplexer, high-frequency switch circuit |
-
1990
- 1990-08-24 JP JP22391590A patent/JPH04105405A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007005951A (en) * | 2005-06-22 | 2007-01-11 | Hitachi Media Electoronics Co Ltd | Transmission circuit, antenna duplexer, high-frequency switch circuit |
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