JPH0410547A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To contrive an increase in the integration of a semiconductor device and the improvement of the driving capacity of the device without generating a punch through by a method wherein an insulating film is etched, a second conductivity type impurity is implanted using sidewalls formed on the side surfaces of a gate electrode as masks and deep high-concentration impurity diffused regions of a second conductivity type are formed in the surface layer of a semiconductor substrate. CONSTITUTION:A gate oxide film 2 is first formed on a silicon substrate consisting of an N-type low-concentration region 6. An impurity-containing polysilicon film is grown on the whole surface and the polysilicon film and the film 2 are subjected to anisotropic etching in order putting a mask on the polysilicon film by a photolithography technique to form a gate electrode 1. Then, a BSG film 3 is formed on the whole surface by a vapor growth. A P-type impurity, boron, being contained in the film 3 is diffused by performing a nitrogen annealing and P-type low-concentration regions 12 are formed. Then, an anisotropic etching is performed on the film 3 and sidewalls 3 consisting of the film 3 are respectively formed on the side surfaces of the electrode 1. Boron is ion-implanted using the sidewalls 3 as masks and P-type high-concentration regions 5, which are used as a source and a drain, are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a transistor (MOS).

[Prior Art] A conventional method for manufacturing a P-type MO5) transistor is shown in Figure 2 (a).
) and (b).

As shown in FIG. 2A, first, a gate oxide film 2 having a thickness of about 200 wafers is formed on a silicon substrate consisting of a lightly doped n-type region 6. Then, polysilicon containing impurities is grown over the entire surface, and the gate polysilicon electrode 1 is formed by masking the polysilicon by photolithography and performing anisotropic etching. Next, boron ions are implanted at an energy of 15 keV and a dose of I x 1013/cTn2 to form a low concentration p-type head region 4.

Next, as shown in FIG. 1B, an oxide film is grown in a vapor phase over the entire surface, and anisotropic etching is performed to form an oxide film sidewall 7 on the side surface of the electrode 1. Then, the boron energy is 30 keV and the dose is 1×1015/cT1.
Ion implantation is performed in step 12 to form heavily doped p-wall regions 5 as sources and drains.

[Problems to be Solved by the Invention] The gate length of MOS (MOS) transistors tends to be further reduced in order to achieve higher integration and improve drive capability. on the other hand,
Due to the short channel effect when the gate length is reduced, there is a certain limit (approximately 0.7 μm) to the gate length in conventional manufacturing methods. The challenge is to raise this limit, that is, to ensure that the transistor operates normally without bunch-through between the source and train even if the gate length is further shortened.

Here, the main cause of the short channel effect is that the electric field generated from the train reaches the source, which causes current to flow between the source and drain, making switching by the gate impossible. An LD interposed between the channel and the source/drain is applied to the electric field generated from this drain.
The D region has a large influence, and the deeper the LDD region has a junction with the semiconductor substrate, the easier the drain electric field can reach the source.

The present invention has been made based on the above findings, and an object of the present invention is to provide a method for manufacturing a semiconductor device that achieves high integration and improved drive capability without causing bunch-through.

[Means for Solving the Problems] A method for manufacturing a semiconductor device of the present invention includes a step of forming a gate electrode on the surface of a semiconductor substrate of a first conductivity type via a gate insulating film, and adding an impurity of a second conductivity type. forming an insulating film containing on the surface of the semiconductor substrate; diffusing impurities from the insulating film to form a shallow low concentration impurity diffusion region of a second conductivity type in the surface layer of the semiconductor substrate; A step of etching an insulating film to form a sidewall on the side surface of the gate electrode, and implanting a second conductivity type impurity into the surface layer of the semiconductor substrate using the sidewall as a mask to form a deep high concentration of the second conductivity type. 1. A method of manufacturing a semiconductor device, comprising the step of forming an impurity diffusion region.

(2) forming a gate electrode on the surface of a first conductivity type semiconductor substrate via a gate insulating film; and forming an insulating film containing a second conductivity type impurity on the surface of the semiconductor substrate; etching the insulating film to form a sidewall on the side surface of the gate electrode; and implanting a second conductivity type impurity into the surface layer of the semiconductor substrate using the sidewall as a mask. The method is characterized by including a step of forming a concentrated impurity diffusion region, and a step of diffusing impurities from the sidewall to form a shallow low concentration impurity diffusion region of a second conductivity type in the surface layer of the semiconductor substrate. .

The method for manufacturing a semiconductor device of the present invention also includes the steps of: forming a gate electrode on the surface of a first conductivity type semiconductor substrate via a gate insulating film; and depositing a second conductivity type impurity-containing insulating film on the semiconductor substrate. a step of etching the insulating film to form a sidewall on the side surface of the gate electrode; and a step of implanting a second conductivity type impurity using the sidewall as a mask to form a sidewall on the surface of the semiconductor substrate. a step of forming a deep high concentration impurity diffusion region of a second conductivity type in the layer; and a step of diffusing impurities from the sidewall to form a shallow low concentration impurity diffusion region of the second conductivity type in the surface layer of the semiconductor substrate. It is characterized by including the following.

Embodiment FIGS. 1(a) to 1(c) are vertical sectional views sequentially showing steps according to an embodiment of the present invention.

As shown in Figure (a), first, a gate oxide film 2 with a thickness of about 200 nm is deposited on a silicon substrate consisting of a low concentration n-type region 6.
form. Then, polysilicon containing impurities is grown over the entire surface, and the polysilicon and gate oxide film 2 are sequentially anisotropically etched by photolithography using a mask to form the gate electrode 1.

Next, as shown in FIG. 2(b), a BSGSaO2 film having a thickness of about 2000 nm is formed over the entire surface by vapor phase growth. and,
By performing nitrogen annealing at 900°C for 10 minutes,
The n-type impurity contained in the BSG film 3 is thoroughly diffused to form a low concentration p wall region 12.

Next, as shown in the same figure (C), anisotropic etching is performed using BSGSaO2 to form BSG
Forms a SaO2 id wall.

Then, using the sidewall 3 as a mask, boron ions are implanted at an energy of 30 keV and a dose of lX1015/cTn2 to form a heavily doped p-wall region 5 that will serve as a source and a train.

By performing the above steps, a P-type MO5) transistor can be formed. Note that the nitrogen annealing step may be performed after forming the high-concentration p-wall region 5 to diffuse boron from the sidewall 3 to form the low-concentration p-wall region 12. In short, the low concentration region 12 can be formed by annealing after the BSGSaO2 is formed.

FIG. 3 is a longitudinal cross-sectional view of another embodiment of the present invention.

First, a gate oxide film 2 having a thickness of about 200 yen is formed on a silicon substrate consisting of a low concentration p-wall region 11. Polysilicon containing impurities is grown on the entire surface, the polysilicon is masked by photolithography, and the polysilicon and gate oxide film 2 are anisotropically etched to a thickness of 11 m to form the gate electrode 1.
form.

Next, a film thickness of approximately 200080 PS is applied to the entire surface by vapor phase growth.
A G film 8 is formed. Then, nitrogen annealing was performed at 900°C.
By doing this for 10 minutes, the n-type impurity phosphorus contained in the PSG film 8 is diffused, and a low concentration n-type region 9 is formed as an LDD region.

Anisotropic etching was performed using PSGSaO8, and PSGS
Forms an aO8 id wall. Then, arsenic was irradiated with an energy of 80 keV and a dose of 1×IO”/Il?m.
” to form a high concentration n-type region 10 and use it as a source train. By performing the above steps, N
type MO3) transistor can be formed.

[Effects of the Invention] In the present invention, an LDD region of a MOS transistor is formed by directly diffusing impurities from an insulating film containing impurities such as a BSG film. This enables an LDD region with a shallow junction that cannot be obtained when formed by ion implantation, and short channel effects can be suppressed even if the gate length is shortened.

For example, in the past, the gate length was 0.7μ due to the short channel effect.
The gate length was previously limited to 0.48 m, but now it is possible to shorten the gate length to about 0.48 m. Therefore, according to the present invention, it is possible to manufacture a semiconductor device that achieves high integration and improved driving ability without causing any problems in the performance of the device.

[Brief explanation of drawings]

FIGS. 1(a) to (c) are vertical cross-sectional views sequentially showing steps according to an embodiment of the present invention, FIGS. 2(a) and (b) are longitudinal cross-sectional views sequentially showing steps of the prior art, and FIGS. FIG. 3 is a longitudinal section showing a process according to another embodiment of the present invention. 1 ・ 2 ・ 3 ・ 4 ・ 5φ 6 7 8 9 ・Gate electrode, ・Gate oxide film, ・BSG film, ・Low concentration p wall region, ・High concentration p wall region, ・Low concentration n type region , - Oxide film, - PSG film, - Low concentration n-type region, - High concentration n-type region, - Low concentration p-type head region, - Low concentration p-type head region.

Claims (2)

[Claims] (1) forming a gate electrode on the surface of a first conductivity type semiconductor substrate via a gate insulating film; and forming an insulating film containing a second conductivity type impurity on the surface of the semiconductor substrate; Diffusing impurities from the insulating film to form a shallow low concentration impurity diffusion region of a second conductivity type in the surface layer of the semiconductor substrate, and etching the insulating film to form sidewalls on the side surfaces of the gate electrode. and a step of implanting a second conductivity type impurity using the sidewall as a mask to form a second conductivity type deep high concentration impurity diffusion region in the surface layer of the semiconductor substrate. A method for manufacturing a semiconductor device. (2) forming a gate electrode on the surface of a first conductivity type semiconductor substrate via a gate insulating film; and forming an insulating film containing a second conductivity type impurity on the surface of the semiconductor substrate; etching the insulating film to form a sidewall on the side surface of the gate electrode; and implanting a second conductivity type impurity into the surface layer of the semiconductor substrate using the sidewall as a mask. The method is characterized in that it includes a step of forming a concentrated impurity diffusion region, and a step of diffusing impurities from the sidewall to form a shallow low concentration impurity diffusion region of a second conductivity type in the surface layer of the semiconductor substrate. A method for manufacturing a semiconductor device.