JPH0410743B2 - - Google Patents

Info

Publication number
JPH0410743B2
JPH0410743B2 JP60241159A JP24115985A JPH0410743B2 JP H0410743 B2 JPH0410743 B2 JP H0410743B2 JP 60241159 A JP60241159 A JP 60241159A JP 24115985 A JP24115985 A JP 24115985A JP H0410743 B2 JPH0410743 B2 JP H0410743B2
Authority
JP
Japan
Prior art keywords
wiring board
chip
sealing resin
resin layer
electronic circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60241159A
Other languages
English (en)
Japanese (ja)
Other versions
JPS62101053A (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP60241159A priority Critical patent/JPS62101053A/ja
Publication of JPS62101053A publication Critical patent/JPS62101053A/ja
Publication of JPH0410743B2 publication Critical patent/JPH0410743B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/075Connecting or disconnecting of bond wires
    • H10W72/07541Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP60241159A 1985-10-28 1985-10-28 薄型電子回路ユニツト Granted JPS62101053A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60241159A JPS62101053A (ja) 1985-10-28 1985-10-28 薄型電子回路ユニツト

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60241159A JPS62101053A (ja) 1985-10-28 1985-10-28 薄型電子回路ユニツト

Publications (2)

Publication Number Publication Date
JPS62101053A JPS62101053A (ja) 1987-05-11
JPH0410743B2 true JPH0410743B2 (2) 1992-02-26

Family

ID=17070137

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60241159A Granted JPS62101053A (ja) 1985-10-28 1985-10-28 薄型電子回路ユニツト

Country Status (1)

Country Link
JP (1) JPS62101053A (2)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6124546A (en) * 1997-12-03 2000-09-26 Advanced Micro Devices, Inc. Integrated circuit chip package and method of making the same
JP5343315B2 (ja) * 2006-12-20 2013-11-13 富士通株式会社 実装構造及び半導体装置
JP6602255B2 (ja) * 2016-05-09 2019-11-06 オリンパス株式会社 医療機器用電子基板

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58182854A (ja) * 1982-04-21 1983-10-25 Hitachi Ltd レジン封止型半導体装置およびその製造方法
JPS5988853A (ja) * 1982-11-12 1984-05-22 Nec Corp Lsiパツケ−ジ

Also Published As

Publication number Publication date
JPS62101053A (ja) 1987-05-11

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term