JPH04107828A - Reducing method for dislocation in compound semiconductor layer - Google Patents

Abstract

PURPOSE:To make it possible to have a low dislocation density in the areas where devices are created by adding energy to certain areas of a semiconductor layer during the cooling process of bringing a compound semiconductor layer to room temperature after growth to make transition movement or propagation easier. CONSTITUTION:A silicon substrate is placed in the reaction tube of an MOCVD system and after cleaning a low growth temperature GaAs buffer layer is formed by supplying AsH3 and TMG while maintaining a temperature at 400 deg.C. Next, the temperature is raised to 700 deg.C and a GaAs layer is formed by supplying AsH3 and TMG. After that, the material is cooled to room temperature. During cooling, energy is added to certain areas of the GaAs layer to make movement and propagation easier. In order to achieve this, an electron beam is applied to these areas. Since the movement active energy of the area 13 of the GaAs layer 11 which is irradiated with an electron beam is higher than that of the area 15 which is not irradiated, it is easier for transition movement to occur or for new transitions to take place and stress is alleviated. As a result, transition propagation in the area 15 decreases compared with conventional methods.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for reducing dislocations in a compound semiconductor layer grown on a silicon substrate.

(Prior art) If it is possible to grow a compound semiconductor such as GaAs on a silicon substrate, it will not only be possible to obtain a compound semiconductor substrate with an unprecedentedly large area, but also to combine the characteristics of silicon with those of compound semiconductors. We can expect to see the realization of useful semiconductor equipment wealth.

Methods for growing GaASN on a silicon substrate include MBE (molecular beam epitaxy) or MOCVD.
An intermediate layer such as Gem is grown on a silicon substrate using the (organometallicization!￥!vapor phase growth) method, and GaAs1L is grown on this layer.
A method of growing a GaAs layer in two stages, a method of growing a GaAs layer directly on a silicon substrate using two stages of growth temperature (hereinafter referred to as a two-stage growth method), etc. are known (for example, see the document ``Nikkei Micro Devices J, 1986. 1.pp, 113-127)
.

However, in either method, silicon and GaAs have different coefficients of thermal expansion, so when a sample with a grown GaAs layer is returned to room temperature from the growth temperature (usually around 700°C), the GaAs grown layer has a strong tensile force. Adds stress. Therefore, if the thickness of the GaAs growth layer is made too thick (3 to 4 um or more), cracks will occur in the growth layer.

The above tensile stress is described in the literature ■ (Japanese Journal of Applied Physics).
Journal of Applied Phy
sics), Vol.

27, No. 10 (19B8.10)), G.
Regardless of the growth temperature of the aAs layer, during the cooling process of the sample after GaAs layer growth, the temperature and room temperature before completion of 350"C, at which dislocations within the grown layer no longer move and no new dislocations are generated within the grown layer. This is caused by the difference in thermal expansion coefficient between silicon and GaAs, and at temperatures above the above-mentioned temperature of around 350°C, dislocations move or new dislocations occur within the growth layer to relieve stress. He says he will.

Therefore, no matter how much the dislocations are reduced in the grown layer at the growth temperature, dislocations are generated during the cooling process as described above, and the 8-concentration of the grown layer is reduced.

(Problem to be Solved by the Invention) However, the conventionally known methods for reducing the dislocation density in the GaAs layer are methods such as the following (1) or (2), or a combination of these methods. This method did not focus on the fact that dislocations occur during the process. Therefore, the dislocation density is 10 @/cm2 or more, and a method that can further reduce the dislocation density has been desired.

(2) A method of turning anil around the growth layer at a temperature of around 900°C (for example, see the literature Near Plyte Physics Letters (ADpl, Phys).

Left), 51. I), 130 (1987)).

■・・・InGaAs on the silicon substrate
/ A method of growing a GaAs layer on the finished strained superlattice layer grown using GaAs etc. (for example, literature: Ap
pl, Phys, Lett, ), 46. p, 294
(1985).

This invention has been made in view of these points, and therefore, an object of the invention is to reduce the dislocation density of a compound semiconductor layer grown on a silicon substrate, at least in the region where elements are formed, compared to the conventional method. The purpose is to provide a method.

(Means for Solving Problem M) In order to achieve this object, according to the present invention, in order to reduce dislocations in a compound semiconductor layer grown on a silicon substrate, the following steps are carried out after the growth of the compound semiconductor layer: The method is characterized in that during the cooling process to room temperature, energy is applied to some regions of the compound semiconductor layer to facilitate the movement and generation of dislocations in the regions.

Here, for example, literature (Japanese Journal Applied Physics)
internal of Applied phys
ics) Vol, 20. No, 3゜1981, L, 16
5-168) states that when a GaAs layer is irradiated with an electron beam, dislocations move in the irradiated area. Therefore, in carrying out the present invention, it is preferable to apply the above-mentioned energy to the above-mentioned region during the cooling process by irradiating the above-mentioned region with an electron beam. Of course, the energy source is not limited to an electron beam, and other sources such as a laser beam may be used.

Note that the above-mentioned cooling process that imparts energy refers to the cooling process from the growth temperature of the compound semiconductor layer to room temperature, or, if annealing is performed at a higher temperature than the growth temperature after growth, cooling from this annealing temperature to room temperature. It refers to processes, etc.

Regarding when to apply the above-mentioned energy during the cooling process, it is preferable to apply the energy throughout the entire cooling process. In addition, even if it is partially applied, at least the temperature range in which dislocations move within the growth layer or new dislocations are likely to occur (for example, the temperature range described in the above-mentioned document Like 350℃
(up to the growth humidity range), it is suitable to apply the above-mentioned energy.

(Function) According to the structure of the present invention, after a compound semiconductor layer is grown on a silicon substrate, dislocations may move or occur in some regions of the compound semiconductor layer during the whole or part of the cooling process of the sample. It is said to be in an easy state.

Therefore, during this cooling process, the stress caused by the difference in thermal expansion coefficient between the silicon and compound semiconductor layers becomes concentrated in areas where stress is easily relaxed, that is, in areas where dislocations in the compound semiconductor layer are likely to move and occur. Then, movement of dislocations and new generation of dislocations occur intensively in this region, and the above-mentioned stress is alleviated. Therefore, dislocations are less likely to occur in regions other than the regions where dislocations are easily moved and generated in the compound semiconductor layer, so if these regions are used for device formation, compounds with lower dislocation density than before can be used. This is equivalent to obtaining a semiconductor layer with high quality.

Moreover, if the above-mentioned energy is applied using an electron beam, there is an advantage that this energy can be easily applied to a minute area.

(Embodiment) Hereinafter, embodiments of the dislocation reduction method of the present invention will be described with reference to the drawings, using an example of reducing dislocations in a GaAs layer grown on a silicon substrate.

The GaAs layer can be formed on the silicon substrate by various conventionally known methods, for example, the various methods disclosed in the above-mentioned document (2). When using the two-step growth method using the MOCVD method among the methods disclosed in this document (■), for example, the following steps may be taken, and FIG. 2 is a diagram for explaining the method.
It is a figure showing the temperature profile in the growth method of an example.

First, a silicon substrate (hereinafter sometimes abbreviated as "substrate") is placed in a reaction tube of an MOCVD apparatus.

Next, in order to clean this substrate, hydrogen diluted ASH3 (arsine, 20%) was added at 11005C in the reaction tube.
Heat the board at a temperature of 950°C for 5 minutes while flowing at a flow rate of C (region ■ in Figure 2).Next, reduce the output of the heating snowmaking to zero and heat the board naturally until the temperature of the board reaches 400°C. Cool down (Area 2).

Next, while maintaining the substrate temperature at 400"C (second
Area ■) in the figure, A s Hs and TMG (1-
(limethyl gallium) and A s Hs flow rate i100
SCCM and TMG (7) style II! Flowing for 2 minutes under the condition of 9SCCM, this allows G to be grown at low temperature on the substrate.
An aAs buffer layer is formed.

This low temperature growth buffer layer is a layer for improving the crystallinity of the growth layer. In addition, the temperature of the TMG cylinder is -1
Maintain at 3.5°C (hereinafter the same).

Next, the substrate temperature was raised to 700"C, and while this temperature was maintained (region ■ in Figure 2), AsH3 was added to the reaction tube.
and TMG and %A S Hs flow rate 7#100SCCM
By flowing ASH3 and TMG into the reaction tube for a predetermined period of time at a flow rate of 95 CCM, a GaAs layer of a desired thickness is grown on the low temperature growth buffer layer.

Incidentally, if the film thickness of this GaAs layer is too thick, cracks will occur, so it is preferable to set the film thickness to about 3 to 4 um.

Next, the sample on which the GaAs layer has been grown is cooled to room temperature (region ■ in Figure 2).During this cooling, the dislocation reduction method of the present invention reduces dislocations in some regions of the GaAs layer. Provides energy that facilitates movement and generation. For this purpose, in this embodiment, this region is irradiated with an electron beam having the above energy.

Here, the partial area can be, for example, the following area. FIG. 1 is a diagram for explaining this,
FIG. 2 is a plan view of a GaAs layer grown on a silicon substrate, viewed from above the growth surface.

In this example, GaAs is used to facilitate electron beam scanning.
Assuming a base grain on Layer 1, an electron beam is irradiated to a region of the GaAs layer corresponding to line segment 13 of the base grain. Note that although the base grains are approximately square in this case, they are not limited to square, and may of course be rectangular.

The region 13 of the GaAs layer 11 that is irradiated with the electron beam has a higher activation energy for the movement of dislocations than the region 15 that is not irradiated, so that the movement of dislocations and the generation of new dislocations are more likely to occur. Therefore, the stress caused by the difference in thermal expansion coefficient between the silicon and GaAs layers during the cooling process after the growth of the GaAs layer is
This concentration is concentrated in the easily relaxed portion, that is, the region of the GaAs layer 11 irradiated with the electron beam, and in this region, dislocations move or new dislocations are generated, thereby relieving the stress. Therefore, since the above stress does not affect the region 15 of the GaAs layer that was not irradiated with the electron beam, the occurrence of dislocations in this region is lower than before, and the dislocation density in this region can be reduced to 10'/cm or less. I can expect it.

Therefore, each region 15 of the GaAs layer 11 that has not been irradiated with the electron beam becomes a suitable region for use in device formation.

Note that irradiating a partial region of the GaAs layer with an electron beam is, for example, MOcVD1! An electron beam irradiation device is installed in NIf, and the electron beam emitted from this is used to remove G in the reaction tube.
This can be done by scanning a predetermined area of the aAs layer. The electron beam irradiation is preferably carried out in a high vacuum state within the reaction chamber to prevent electron beam scattering. In this case, in order to maintain the degree of vacuum, it is not possible to flow cooling gas into the reaction vessel, so the cooling of the substrate is performed using, for example, a support rod connected to a substrate mounting table provided in the MOCVD apparatus. This can be done by making part or all of the substrate made of a material with high thermal conductivity, thereby dissipating the heat of the substrate to the outside.

In addition, in the above, an example was explained in which the cooling process is started immediately after growing a GaAs layer on a silicon substrate, but after growing GaAsFl, the cooling process is started at a temperature different from the growth temperature to improve crystallinity. Heat treatment (annealing) may be performed. In such a case, the method of this invention may be applied during the process of cooling the heat-treated finished sample to room temperature.
In this case as well, the same effects as in the tiger embodiment can be obtained.

Further, how long the electron beam is irradiated during the cooling process of the sample is determined depending on the thickness of the GaA three layer, the cooling rate, the desired dislocation density, etc. Specifically, possible modes include irradiating the electron beam continuously during the cooling process, irradiating the electron beam only during a part of the cooling process, and irradiating the electron beam intermittently during the cooling period. .

In the above, the region that provides energy that facilitates the movement and generation of dislocations has been described as a region corresponding to the base line segment of the GaAs layer, but this region is not limited to this example and can be modified depending on the design. It is clear that changes can be made depending on the situation.

In addition, in the above description, the energy that facilitates the movement and generation of dislocations was imparted by electron beam irradiation, but the energy source is not limited to electron beams, and of course, other energy sources may also be used. For example, a laser can be used.

In addition, although the compound semiconductor layer was made of GaAs in the above-mentioned example, the method of the present invention is also expected to be applied when the compound semiconductor layer grown on the silicon substrate is made of other materials (for example, InP, etc.). I can do it.

(Effects of the Invention) As is clear from the above description, according to the method for reducing dislocations in a compound semiconductor layer of the present invention, the compound semiconductor layer is Dislocation movement and
Gives energy to facilitate generation. Therefore, stress caused by the difference in thermal expansion coefficients between silicon and the compound semiconductor layer during the cooling process is applied to the part of the compound semiconductor layer.
dislocations are concentrated in the area and dislocations are generated intensively in that part of the area. Therefore, the region other than this part of the compound semiconductor layer (the region to which the above-mentioned energy was not applied) becomes a layer with fewer dislocations than in the past.

[Brief explanation of drawings]

Figure 1 is a diagram used to explain an example, and Figure 2 is a diagram used to explain a partial region that provides energy that facilitates the movement and generation of dislocations in a compound semiconductor layer. FIG. 11-GaAs layer grown on silicon substrate 13-G
Partial area of aAs layer (electron beam irradiation area) 15-・Electron beam non-irradiation area. Figure 1 for explaining the embodiment of patent applicant Oki Electric Industry Co., Ltd.

Claims (2)

[Claims] (1) In order to reduce dislocations in a compound semiconductor layer grown on a silicon substrate, during the cooling process to room temperature that is performed after the growth of the compound semiconductor layer, some regions of the compound semiconductor layer are A method for reducing dislocations in a compound semiconductor layer, the method comprising applying energy to facilitate movement and generation of dislocations in the region. (2) The method for reducing dislocations in a compound semiconductor layer according to claim 1, wherein the energy is applied to the region by irradiating the region with an electron beam. How to reduce dislocations.