JPH04107858A - Dynamic type semiconductor memory and manufacturing method thereof - Google Patents

Abstract

PURPOSE:To restrain defects such as discontinuity of a fine wiring or the like which is formed on the first surface side of a first semiconductor base by a method wherein a selective electric field effect type transistor is formed by using the first semiconductor base and a capacitor for storing information is formed between the first and second semiconductor bases. CONSTITUTION:A capacitor for storing information comprising a stacked electrode 4 under a first silicon base 1, a silicon nitrided film 6 which is a capacitance insulating film and a plate electrode 7 is formed. A predetermined wiring is formed on an insulating film 15 above the base 1. As a result, even if a size of the capacitance becomes relatively larger by reducing a memory cell, a large steps is not formed on a surface of the insulating film 15 and flatness on the surface of the insulating film 15 is superior. Accordingly, the fine wiring having no detects such as discontinuity on the insulating film 15 or the like can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic semiconductor memory device having a temporary memory capacity and a method for manufacturing the same.

[Prior Art] A dynamic semiconductor memory device (hereinafter referred to as DRAM) includes: - an information storage capacitor for temporally storing information and a selection field effect transistor (hereinafter referred to as MOS);
It is composed of transistors (called transistors). In this case, in order for the DRAM to operate normally, the capacitance value of the information storage capacitor must be greater than or equal to a predetermined value.

However, with the recent increase in the degree of integration of semiconductor devices,
The formation area of an information storage capacitor in a plan view tends to decrease, and it has become difficult to secure a predetermined capacitance value with a planar structure.

For this reason, DRAMs having information storage capacitors with various three-dimensional structures have been proposed, and some of these have already been put into practical use.

FIG. 4 is a sectional view showing an example of such a conventional DRAM. This DRAM structure is called a trench capacitor type memory cell.

A trench 29 is provided in a predetermined region of the silicon substrate 20 . A capacitive insulating film 28 is provided on the bottom and side walls of the trench 29, and a plate electrode 27 is embedded in the trench 29. Note that the capacitor insulating film 26 and the plate electrode 27 extend slightly over the base 20 as well.

Further, around this trench 29, a diffusion region 25 into which impurities are introduced at a high concentration is formed.

A source region 23 and a drain region 24 are formed on the surface of the base body 20 so as to be separated from each other by an appropriate distance. This source region 23 is connected to a diffusion region 25. Further, a gate electrode 22 is formed on the base body 20 between the source region 23 and the drain region 24 with a gate insulating film 21 interposed therebetween.

Base body 20 including plate electrode 27 and gate electrode 22 tops
An insulating film 28 is formed thereon, and predetermined wiring (not shown) is formed on this insulating film 28.

In the DRAM configured in this way, an information storage capacitor is configured by the capacitive insulating film 26, the diffusion region 25, and the plate electrode 27, and the surface area of the counter electrode (plate electrode 27) is large in a small area in plan view. Therefore, a capacitor with a large capacitance value can be obtained. Further, this DRAM has the advantage that the surface of the insulating film 28 on which wiring is to be formed is relatively flat, and fine wiring can be formed thereon.

FIG. 5 is a sectional view showing another conventional DRAM. This DRAM structure is called a stacked capacitor type memory cell.

On the surface of the silicon substrate 30, a source region 33 and a drain region 34 of a selection transistor MO8) are formed at an appropriate distance from each other. A gate insulating film 31 is formed on the base 30 between the source region 33 and the drain region 34.
A gate electrode 32 is formed through the gate electrode.

A stacked electrode 35 is formed on the source region 33. This stacked electrode 35 extends above the gate electrode 32. Further, a capacitive insulating film 86 is formed on the side and top surfaces of the stacked electrode 35. A plate electrode 37 is formed above and on the sides of this capacitive insulation 83B. This plate electrode 37 is covered with an insulating film 38, and predetermined wiring (not shown) is formed on this insulating film 38.

In the DRAM cell configured in this manner, the stacked electrode 35, the capacitive insulating film 36, and the plate electrode 37 constitute a capacitor for storing information. In this DRAM as well, a capacitor with a relatively large capacitance value can be formed in a small area in plan view.

[Problems to be Solved by the Invention] However, the conventional DRAM described above has the following problems. That is, in the case of the trench capacitor type memory cell shown in FIG.
It is necessary to increase the depth of However, although it is not impossible with the current technology to form a trench with a small opening area and a deep depth on the surface of the substrate, it is extremely complicated.

On the other hand, in the case of the stacked capacitor type memory cell shown in FIG. 5, it is necessary to increase the thickness of the stacked electrode 35 in order to downsize the memory cell while ensuring a predetermined capacitance value. However, if the thickness of the stacked electrode 35 is increased, a large step will be formed on the surface of the insulation J [38], making it extremely difficult to form an upper layer structure (particularly fine wiring without defects such as disconnections). become.

As described above, in conventional DRAMs, when memory cells are miniaturized, it becomes extremely difficult to form an information storage capacitor with a predetermined capacitance value, or when forming an information storage capacitor, an insulating film is required. There is a problem in that the flatness of the surface deteriorates, making it difficult to form fine wiring.

The present invention has been made in view of such problems, and includes:
It is easy to manufacture without complicated processes, and the surface of the insulating film on which the wiring is to be formed has excellent flatness, so that fine wiring, etc. can be formed on this insulating film without defects such as disconnections. An object of the present invention is to provide a dynamic semiconductor memory device and a method for manufacturing the same.

[Means for Solving the Problems] A dynamic semiconductor memory device according to the first invention of the present application includes a first semiconductor substrate having first and second surfaces facing each other, and a first semiconductor substrate of the first semiconductor substrate. a selection field effect transistor formed of a source region, a drain region, and a gate electrode disposed on the first surface side; and the source region formed on the second surface side of the first semiconductor substrate. an information storage capacitor constituted by a stacked electrode electrically connected to the stacked electrode, a capacitive insulating film deposited on the stacked electrode, and a plate electrode disposed opposite to the stacked electrode via the capacitive insulating film; , and a second semiconductor substrate facing the first semiconductor substrate with the capacitor sandwiched therebetween.

In the dynamic semiconductor memory device according to the second invention of the present application, the selection field effect transistor includes a drain region disposed on the first surface side of the first semiconductor substrate, a second
The source region is formed on the side of the drain region, and the gate electrode is formed from the surface of the drain region toward the source region, and the other structure is the same as that of the first invention described above.

A method for manufacturing a dynamic semiconductor memory device according to a third aspect of the present application includes forming a first insulating film on the second surface of a first semiconductor substrate having first and second surfaces facing each other. selectively forming a contact hole in the first insulating film; burying the contact hole with a polycrystalline silicon film doped with impurities; a step of diffusing impurities to form an impurity diffusion region and selectively extending the polycrystalline silicon film onto the surface of the first insulating film to form a sassete stacked electrode; a step of forming a second insulating film, a step of forming a plate electrode made of a polycrystalline silicon film on the surface of the second insulating film, and a step of forming a third insulating film on the surface of the plate electrode. a step of bonding a second semiconductor substrate; a step of forming a gate electrode on the first surface side of the first semiconductor substrate via a gate insulating film; The method is characterized by comprising a step of selectively introducing impurities into the substrate to form a drain region and a source region reaching the impurity diffusion region.

A method for manufacturing a dynamic semiconductor memory device according to a fourth invention of the present application includes a first insulating film, an impurity diffusion region on the second surface side of a first semiconductor substrate, and
a step of forming a stacked electrode, a second insulating film, and a plate electrode; a step of bonding a second semiconductor substrate on the surface of the plate electrode via a third insulating film;
a step of selectively introducing impurities into the first surface side of the semiconductor substrate to form a source region; a step of forming a trench from the surface of the source region toward the impurity diffusion region; The method is characterized by comprising a step of embedding a gate electrode through a gate insulating film.

[Function] In the present invention, a selection field effect transistor is formed using the first semiconductor substrate.

Furthermore, an information storage capacitor constituted by a stacked electrode, a capacitive insulating film, and a plate electrode is arranged between the first semiconductor substrate and the second semiconductor substrate. Therefore, the dynamic semiconductor memory device according to the present invention has a structure in which the information storage capacitor is substantially embedded between the first semiconductor substrate and the second semiconductor substrate, and the It is possible to avoid forming a large step on the first surface side of one semiconductor substrate due to the information storage capacitor. Thereby, fine wiring without defects can be formed on the first surface side of the first semiconductor substrate.

Further, in the method of the present invention, the second
A stacked electrode, a second insulating film, and a plate electrode are formed on the surface side to constitute an information storage capacitor. In this case, the stacked electrode is formed of a polycrystalline silicon film into which impurities are introduced, and the polycrystalline silicon film forms a contact hole of the first insulating film formed on the second surface of the first semiconductor substrate. , the impurity is diffused from the polycrystalline silicon film into the first semiconductor substrate to form an impurity diffusion region. Then, for example, the surface of the plate electrode is flattened by mirror polishing, and a second semiconductor substrate whose surface has been mirror polished is bonded to the plate electrode. Thereby, the information storage capacitor has a structure in which it is substantially embedded between the first semiconductor substrate and the second semiconductor substrate.

On the other hand, a source region, a drain region, and a gate electrode are formed on the first surface side of the first semiconductor substrate to provide a selection field effect transistor; A selection field effect transistor, which is a vertical transistor, is provided by forming a drain region on the side and using the impurity diffusion region as a source region.

As described above, the method of the present invention does not require the extremely complicated process of forming a trench with a narrow opening and a deep depth, as is required for conventional trench capacitor type memory cells. A storage device can be easily manufactured.

[Embodiments] Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a sectional view showing a dynamic semiconductor memory device according to a first embodiment of the present invention.

A silicon oxide film 8 is formed on the second single crystal silicon substrate 9, and a plate electrode 7 made of polycrystalline silicon is formed on this silicon oxide film 8. This plate electrode 7 is selectively provided with recesses. A silicon nitride film 6 is formed on the plate electrode 7 and on the side and bottom surfaces of the recess. A stacked electrode 4 made of polycrystalline silicon is embedded in the recess. An insulating film 2 is formed on the stacked electrode 4. A contact hole 3 is selectively provided in this insulating film 2, and a stacked electrode 4 extends into this contact hole 3.

A first semiconductor substrate 1 is provided on the insulating film 2 .

A source region 13 and a drain region 14 are selectively formed in the first semiconductor substrate 1, respectively. This source region 13 is electrically connected to the stacked electrode 4 via the contact hole 3 . Further, a gate insulating film 11 is formed on the base 1 between the source region 13 and the drain region 14.
A gate electrode 12 is selectively formed through the gate electrode. Furthermore, an insulating film 1 is formed on the base 1 including the gate electrode 12.
5 is formed, and predetermined wiring (not shown) is formed on this insulating film 15.

In this embodiment, an information storage capacitor consisting of a stacked electrode 4, a silicon nitride film 6 serving as a capacitive insulating film, and a plate electrode 7 is formed below the first silicon substrate 1. A predetermined wiring is formed on the insulating film 15 above the base 1. Therefore, even if the size of the capacitor becomes relatively large by reducing the size of the memory cell, it is possible to avoid forming a large step on the surface of the insulating film 15, and the surface flatness of the insulating film 15 is excellent. There is. Therefore, fine wiring without defects such as disconnections can be formed on the insulating film 15.

FIGS. 2A to 2C are cross-sectional views showing the method for manufacturing the above-mentioned dynamic semiconductor memory device in order of steps. However, for ease of explanation, FIGS. 2(a) and 2(b) are shown upside down in the vertical direction with respect to FIG. 1.

First, as shown in FIG. 2(a), an insulating film 2 is formed on a first p-type single crystal silicon substrate 1, and contact holes 3 are selectively provided in this insulating film 2. As shown in FIG.

Thereafter, a polycrystalline silicon film containing phosphorus as an n-type impurity is grown from the surface of the base body 1 exposed in the contact hole 3, and this polycrystalline silicon film is patterned into a predetermined shape to obtain a stacked electrode 4. At the same time as this stacked electrode 4 is manufactured, phosphorus is diffused from the polycrystalline silicon film into the silicon substrate 1, and an n-type diffusion region 5 is selectively formed on the surface of the substrate 1. Next, a silicon nitride film 6 is grown over the entire surface. After that, this silicon nitride film 6
Plate electrode 7 is formed by depositing a polycrystalline silicon film thereon to a thickness that completely buries the space between stacked electrodes 4 .

Next, as shown in FIG. 2(b), the surface of the plate electrode 7 is polished to a flat surface. Thereafter, the surface of this plate electrode 7 is thermally oxidized to form a silicon oxide film 8. Next, a second silicon substrate 9 whose surface has been mirror-polished is placed on this silicon oxide film 8. Then, the second silicon substrate 9 is bonded onto the silicon oxide film 8 by performing heat treatment at a high temperature.

Next, as shown in FIG. 2C, the surface of the base 1 that is not in contact with the insulating film 2 is polished to give the base 1 a predetermined thickness, and this surface is mirror polished.

Next, as shown in FIG.
O8) A selection MO8) transistor is formed in the same manner as in the manufacturing of the transistor. That is, a gate electrode 2 is formed in a predetermined pattern on the surface of the substrate 1 that has been mirror-polished in the previous step via a gate insulator M1, and using this gate electrode 12 as a mask, n-type impurities are introduced into the surface of the substrate 1. Thus, the source region 13 and drain region 14 are formed in a self-aligned manner. In this case, the diffusion region 5 is connected to the source region 13 and becomes a part of the source region 13 . Thereby, the source region 13 and stacked electrode 4 are electrically connected.

After that, an interlayer insulating film 15 is formed on the entire surface. Then, wiring for leading out electrodes and the like are formed on this interlayer insulating film 15. In this case, the drain region 14 is connected to the bit line,
The gate electrode 12 is connected to a word line, and the plate electrode 7 is connected to a wiring on an interlayer insulating film 15 as a counter electrode of a capacitor. As a result, a dynamic semiconductor memory device is completed.

In this embodiment, as described above, there is no need for a step of forming a trench with a narrow opening and a deep depth, and the highly integrated dynamic semiconductor memory device having the structure shown in FIG. It can be easily manufactured.

FIG. 3 is a sectional view showing a dynamic semiconductor memory device according to a second embodiment of the present invention.

This embodiment differs from the first embodiment in that the structure of the selection MO8) transistor is different, and the other configurations are basically the same as the first embodiment. Components that are the same as those in FIG. 1 are given the same reference numerals, and detailed explanation thereof will be omitted.

An information storage capacitor consisting of a stacked electrode 4, a silicon nitride film 6, and a plate electrode 7 is formed below the single crystal silicon substrate 1, as in the first embodiment. Further, a source region 1 is provided on the bottom surface of the single crystal silicon substrate 1.
3a is selectively formed, and this source region 13a
are electrically connected to stacked electrodes 4 through contact holes 3 provided in insulating film 2 . Furthermore, a drain region 14 is selectively formed on the upper surface of the base 1.

A trench 16 is selectively formed in the base 1, reaching the source region 13a from the upper surface thereof. A gate electrode 12a is embedded in this trench 16 with a gate insulating film 11a interposed therebetween. This gate electrode 12
a extends slightly above the base 1. An insulating film 15a is formed on the base 1 including the gate electrode 12a, and a predetermined wiring (not shown) is formed on the insulating film 15a.
is formed.

In this embodiment as well, the surface of the insulating film 15a is substantially flat regardless of the size of the information storage capacitor. Therefore, fine wiring without defects can be formed on this insulating film 15a.

Next, a method of manufacturing the dynamic semiconductor memory device according to this embodiment will be explained. In the method of this embodiment, the manufacturing steps up to intermediate steps are the same as those described in the first embodiment, so the explanation will begin from the end of the steps shown in FIG. 2(C).

First, as shown in FIG. 2(C), an information storage capacitor is formed between the first and second single crystal silicon substrates 1 and 9, and a diffusion region 5 is selectively formed in the substrate 1.
As shown in FIG. 3, n-type impurities are introduced into the surface of the substrate 1 to form a drain region 14a. Furthermore, the n-type diffusion region 5 is used as a source region 13a, and a trench 16 is formed that reaches this source region 13a from the surface of the base 1.

Next, a gate insulating film 11a is formed on the bottom wall and sidewalls of this trench 1e. Then, trench 16 is filled with polycrystalline silicon to form gate electrode 12a. After that, an interlayer insulating film 15a is formed on the entire surface.

Next, predetermined wiring is formed on this insulating film 15a.

As a result, a dynamic semiconductor memory device having the above-described structure is completed.

The selection MO3) transistor of the dynamic semiconductor memory device thus manufactured is a vertical transistor in which the n-type diffusion region 5 formed at the same time as the stacked electrode 4 serves as the source region 13a.

Therefore, in this embodiment, the stacked electrode 4 of the information storage capacitor and the source region 13a of the selection MOS transistor are necessarily electrically connected. Also in the method of this embodiment, a highly integrated dynamic semiconductor memory device having an information storage capacitor with a predetermined capacitance value can be easily manufactured.

[Effects of the Invention] As explained above, according to the present invention, a selection field effect transistor is formed using a first semiconductor substrate, and the first semiconductor substrate and the second semiconductor substrate Since an information storage capacitor is formed between It is possible to prevent a large step from being formed on the opposing first surface side due to the capacitor. Therefore, defects such as disconnection of fine wiring formed on the first surface side of the first semiconductor substrate can be suppressed.

Further, according to the method of the present invention, there is no complicated process such as forming a trench with a narrow opening and a deep depth.
A highly integrated dynamic semiconductor memory device having the above structure can be easily manufactured.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a dynamic semiconductor memory device according to a first embodiment of the present invention, FIGS. 2(a) to (C) are sectional views showing the manufacturing method thereof in the order of steps, and FIG. A cross-sectional view showing a dynamic semiconductor memory device according to a second embodiment of the present invention, FIG. 4 is a cross-sectional view showing an example of a conventional dynamic semiconductor memory device, and FIG. 5 is a cross-sectional view showing an example of a conventional dynamic semiconductor memory device. FIG. 3 is a cross-sectional view showing a storage device. 1.9.20,30; Silicon base, 2,15°15a
+ 26+ 28+ 36+ 38; Insulating film, 3; Contact hole, 4, 35; Stacked' [pole, 5°25; n
Type diffusion region, 6; Silicon nitride film, 7°27.37; Plate electrode, 8; Silicon oxide film, 11, lla, 21
．． 31; Gate insulating film, 12° 12a, 22.32; Gate electrode, 13.13a. 23.33; Source region, 14, 14a, 24°34;
Drain region, 16; trench

Claims (4)

[Claims] (1) A first semiconductor substrate having first and second surfaces facing each other, and a source region, a drain region, and a gate electrode disposed on the first surface side of the first semiconductor substrate. a selection field effect transistor configured, a stacked electrode formed on the second surface side of the first semiconductor substrate and electrically connected to the source region, and a capacitive insulator deposited on the stacked electrode. an information storage capacitor constituted by a film and a plate electrode disposed opposite to the stacked electrode with the capacitive insulating film interposed therebetween;
A dynamic semiconductor memory device comprising: a second semiconductor substrate facing the first semiconductor substrate with the capacitor in between. (2) a first semiconductor substrate having first and second surfaces facing each other, a drain region disposed on the first surface side of the first semiconductor substrate, and a drain region disposed on the second surface side of the first semiconductor substrate; a selection field effect transistor configured with a source region disposed on the surface of the source region and a gate electrode formed from the surface of the drain region toward the source region; and the second surface side of the first semiconductor substrate. The stacked electrode is formed in a stacked electrode and is electrically connected to the source region, a capacitive insulating film is deposited on the stacked electrode, and a plate electrode is disposed opposite to the stacked electrode with the capacitive insulating film interposed therebetween. 1. A dynamic semiconductor memory device comprising: an information storage capacitor; and a second semiconductor substrate facing the first semiconductor substrate with the capacitor sandwiched therebetween. (3) forming a first insulating film on the second surface of the first semiconductor substrate having first and second surfaces facing each other; forming a contact hole; burying the contact hole with a polycrystalline silicon film into which an impurity is introduced; diffusing the impurity from the polycrystalline silicon film into the first semiconductor substrate to form an impurity diffusion region; a step of selectively extending the polycrystalline silicon film on the surface of the first insulating film to form a stacked electrode; a step of forming a second insulating film on the surface of the stacked electrode; and a step of forming a second insulating film on the surface of the stacked electrode. a step of forming a plate electrode made of a polycrystalline silicon film on the surface of the insulating film; a step of bonding a second semiconductor substrate on the surface of the plate electrode via a third insulating film; forming a gate electrode on the first surface side of the semiconductor substrate via a gate insulating film; and using the gate electrode as a mask, selectively introducing impurities into the first semiconductor substrate to form a drain region and the first semiconductor substrate. 1. A method of manufacturing a dynamic semiconductor memory device, comprising the step of forming a source region that reaches an impurity diffusion region. (4) forming a first insulating film on the second surface of the first semiconductor substrate having first and second surfaces facing each other; forming a contact hole; burying the contact hole with a polycrystalline silicon film into which an impurity is introduced; diffusing the impurity from the polycrystalline silicon film into the first semiconductor substrate to form an impurity diffusion region; a step of selectively extending the polycrystalline silicon film on the surface of the first insulating film to form a stacked electrode; a step of forming a second insulating film on the surface of the stacked electrode; and a step of forming a second insulating film on the surface of the stacked electrode. a step of forming a plate electrode made of a polycrystalline silicon film on the surface of the insulating film; a step of bonding a second semiconductor substrate on the surface of the plate electrode via a third insulating film; forming a source region by selectively introducing impurities into the first surface side of the semiconductor substrate; forming a trench from the surface of the source region toward the impurity diffusion region; 1. A method for manufacturing a dynamic semiconductor memory device, comprising the steps of: embedding a gate electrode through a gate insulating film.