JPH04108270A - Video signal encoding device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a video signal encoding device that performs high-efficiency encoding, which is a means of reducing the amount of image data in order to record and transmit video signals. be.

One of the conventional video signal encoding devices is one that divides the screen into small blocks. Furthermore, regarding the processing of divided blocks, there are two types: one that performs processing on a frame basis and one that performs processing on a field basis. In the current television system, interlaced scanning called interlacing is performed on the screen for each scanning line, and when processing is performed frame by frame rather than field by field, the distance between the scanning lines is shorter and the correlation is reduced. Therefore, when performing predictive coding or orthogonal transformation on a still image, it is more efficient to process it frame by frame. In this case, pixels are shifted every other scanning line by the distance moved in one field scanning time, resulting in low correlation and poor efficiency.

In order to solve such problems, a method has been devised in which the processing method within a block is compared between fields and within a field and switched to the more efficient method.

FIG. 3 is a configuration diagram of an encoding device and a decoding device for explaining a conventional video signal encoding device.

In the figure, (a) is a block diagram of the encoding device, in which 1 is a buffer memory, 2 and 3 are block generators, 45 is an orthogonal transformer, 6.7 is a quantizer, and 8 and 9 are encoders. , 10 is a comparator.

The images stored in buffer memory 1 can be saved in professional mode.

It is divided into blocks of 8 pixels vertically by 8 pixels horizontally using fixture 2.3. Furthermore, as shown in Figure 2, a block of 8 pixels vertically x 8 pixels horizontally is divided into upper and lower halves every 4 scanning lines for intra-frame processing, and divided into 2 parts every other scanning line for intra-field processing, resulting in two blocks each. Vertical 4 west elements x horizontal 8 i! I elementary professional
create a link.

The signals of each block are orthogonally transformed by an orthogonal transformer 4.5, requantized by quantizers 6 and 7, and encoded by an encoder 8.9.

The comparator 10 compares the code amounts of the inter-field processing and the intra-field process in units of 8×8 pixel blocks, and selects the one with the smaller code amount. A flag indicating whether inter-field processing or intra-field processing is selected is also output.

FIG. 3(b) is a block diagram of the decoding device. In the figure, 11 is a buffer memory, 12 is a decoder, 13 is an inverse quantizer, 14 is an orthogonal transformer, 15 is an inverse block generator,
16 is a selector.

After the encoded input is stored in the buffer memory 11, it is decoded by the decoder 12, and subjected to the inverse operation of the encoder and quantizer on the encoding device side by the inverse quantizer 13,
0 selector 16 which is returned to the video signal by the orthogonal transformer 14
selects either inter-field processing or intra-field processing from the flag, and the deblocker 15 returns the decoding result to the pixel array selected at the time of encoding and outputs it.

Problems to be Solved by the Invention However, in the conventional technology, in order to select between inter-field processing and intra-field processing, it is necessary to encode and quantize both, which increases calculation time.

There is a problem in terms of circuit scale. Especially to increase encoding efficiency? This problem becomes more serious as the encoder that performs the H.31S1i processing is used.

In view of the above, an object of the present invention is to provide a video signal encoding device with a simpler configuration and higher encoding efficiency.

Means for Solving the Problems The present invention provides blocking means for dividing a screen into blocks, means for calculating a difference signal between a signal in each divided block and a signal of a previous frame, and a means for calculating a difference signal between a signal in each divided block and a signal in a previous frame. means for comparing one or more constants with a preset number of intervals; and two means for performing encoding processing within each block between fields or within a field based on the relationship between the number of intervals of the difference signal and the constants. A video signal encoder characterized by comprising means for selecting one of the two types of processing, and means for encoding according to the selected processing! It is.

Effect The present invention uses the above-mentioned means to convert the inter-frame difference signal to i.
l! ! By comparing the values, it is possible to switch the processing method between fields, within fields, etc. before actually performing complex processing such as conversion, quantization, and coding, and to compare the actual conversion, quantization, and coding for each block. The number of times the conversion process is performed can be suppressed to one, and a video signal encoding device with a simpler configuration, short calculation time, and high encoding efficiency can be obtained.

Embodiment FIG. 1 is a block diagram of an encoding apparatus for explaining a first embodiment of the present invention. 17 is a frame memory, 18 is a buffer memory, 19.20 is a block generator, 21 is a subtracter, 22 is a comparator, 23 is an orthogonal transformer, 24 is a quantizer, and 25 is an encoder.

The frame memory 17 stores a signal of one frame before the frame to be encoded.

The signal of the frame to be encoded stored in the buffer memory for one day is divided into blocks of 8 pixels vertically by 8 pixels horizontally by a block generator 19. Retrieving from the frame memory 17 the signal of the block one frame before the same pixel position as the signal of each of the divided blocks;
A subtracter 21 obtains a difference. A comparator 22 compares the sum of the absolute values of the obtained difference values and the dark value.

If the inter-frame difference is large, it is generally considered that the image within the block is moving, so if it is equal to or greater than the darkness value, it is determined that it is moving, and intra-field processing is selected. If it is below the threshold, it is determined that it has stopped, and inter-field processing is selected.

When inter-field processing is selected, a block of Bij pixels vertically x 8 pixels horizontally is divided into upper and lower halves every 4 scanning lines as shown in Figure 2, and when intra-field processing is selected, one scan is performed. The block is divided into two every other line, and the block generator 20 creates two blocks each having 4 pixels in the vertical direction and 8 pixels in the horizontal direction.

The signal of the selected block is transformed by the orthogonal transformer 23, requantized by the quantizer 24, and then requantized by the encoder 2.
5.

Actual orthogonal transformation and quantization compared to conventional examples.

Rather than performing complex encoding processing between fields and within fields, orthogonal transformation is performed only once after selection.
It is only necessary to perform quantization and encoding, and the device configuration can be made smaller and calculation time can be shortened.

In the above explanation, the size of the block to be divided is 4 x 8 pixels, and the size of the comparison between frames is 8 x 8! Basically, these sizes are arbitrary. Furthermore, although the block division method shown in FIG. 2 was used for inter-field processing and intra-field processing, these division methods may be arbitrary.

In addition, although we compared the sum of the absolute values of the darkness value and the inter-frame difference value, other functions such as the sum of the squares of the inter-frame difference values may be used, and the comparison method is arbitrary. One or more may be prepared and one of the judgments may be selected.

As described in detail, according to the present invention, it is possible to obtain a video signal encoding device with a simpler configuration and higher encoding efficiency.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an encoding device according to a first embodiment of the present invention, FIG. 2 is an explanatory diagram of a method of dividing blocks and a method of comparing processes within a block, and FIG. 3(a) 1 is a block diagram showing the configuration of a conventional encoding device, and Φ) in the same figure is a block diagram showing the configuration of a conventional decoding device. 1.18...Buffer memory, 2,3,19°20...Blocker, 4,5,14.23.
... Orthogonal transformer, 6.7.24 ... Quantizer, 8.925 ... Encoder, 12 ...
...Decoder, 13...Inverse quantizer, 15...
...Reverse production, fixtures, 16...Selector, 1
7...Frame memory, 22...Comparator, 21...Subtractor. Name of agent: Patent attorney Haruaki Ogata and 2 others Figure r! R No. 1 Class" Pro 12 Henepus 7" S-t F Diagram

Claims (3)

[Claims] (1) Blocking means for dividing the screen into blocks, means for calculating a difference signal between the signal in each divided block and the signal of the previous frame, and a preset value based on the relationship between the difference signals. or means for comparing a plurality of constants, and means for selecting one of two cases in which encoding processing within each block is performed between fields or within a field based on the relationship between the function of the difference signal and the constant. 1. A video signal encoding device comprising: and means for encoding by the selected processing. (2) A method for calculating a difference signal between a signal in each divided block and a signal in a block located at the same pixel position as each block in the previous frame. 1) The video signal encoding device described above. (3) Difference between the signal in each divided block and the signal in a block located at a position shifted by an arbitrary pixel in the vertical and horizontal directions from the corresponding position in each block in the previous frame 2. The video signal encoding device according to claim 1, further comprising means for calculating the signal.