JPH04109663A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH04109663A JPH04109663A JP2229475A JP22947590A JPH04109663A JP H04109663 A JPH04109663 A JP H04109663A JP 2229475 A JP2229475 A JP 2229475A JP 22947590 A JP22947590 A JP 22947590A JP H04109663 A JPH04109663 A JP H04109663A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- transistor
- voltage
- semiconductor device
- transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000003990 capacitor Substances 0.000 claims abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は低電圧単一電源EEPROM等、昇圧回路を
有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a booster circuit, such as a low voltage single power supply EEPROM.
本発明は、昇圧回路を有する半導体装置において、So
l基板上に、昇圧回路のトランジスタを形成することに
より、基板電流がなくなり外部入力電圧の十倍以上にも
及ぶ昇圧を効率的に行えるようにしたものである。The present invention provides a semiconductor device having a booster circuit, in which So.
By forming the transistors of the booster circuit on the l substrate, there is no substrate current and it is possible to efficiently boost the voltage to more than ten times the external input voltage.
第3図に示すような、シリコン基板上に形成されたトラ
ンジスタを、例えば第2図のような昇圧回路に用いてい
た。従って、01〜CNのキャパシタを順番に、■。の
電圧を外部から1−Nへと順番にかけることにより、そ
れぞれのキャパシタに蓄えられた電荷で、■1〜VN(
V+ <Vz・・・>VN) と、順に電圧をあげて高
電圧を得ていた。A transistor formed on a silicon substrate as shown in FIG. 3 has been used, for example, in a booster circuit as shown in FIG. Therefore, the capacitors 01 to CN are connected in order. By sequentially applying the voltage from the outside to 1-N, the electric charge stored in each capacitor is used to convert ■1 to VN (
V+ <Vz...>VN), the voltage was increased in order to obtain a high voltage.
基板電流が存在するため、■8に近づくにつれ昇圧効率
が悪くなり、例えば、■。= 1.5M程度で、20(
V)の電圧を得ることは困難があった。Because of the presence of substrate current, the boost efficiency deteriorates as it approaches ■8, for example, ■. = about 1.5M, 20(
It was difficult to obtain a voltage of V).
上記問題点を解決するために、この発明は各トランジス
タを、Sol構造上に形成することにより、基板及び他
のトランジスタと酸化膜で完全に絶縁するようにした。In order to solve the above problems, the present invention forms each transistor on a Sol structure so that it is completely insulated from the substrate and other transistors by an oxide film.
上記のように、各トランジスタを基板及び他のトランジ
スタと完全に絶縁することにより、基板電流をなくすこ
とができるため、効率よく電圧を増加することができる
ようにしたものである。As described above, by completely insulating each transistor from the substrate and other transistors, the substrate current can be eliminated, so that the voltage can be increased efficiently.
第1図に示したように、Sol基板上に、昇圧回路用ト
ランジスタを形成する。例えば素子分離法にLOCO3
法を用いた時、第1図に示したような断面形状を持つト
ランジスタとなる。すると、基板から電気的に完全に分
離した形となる。従って例えば第2図に示したような回
路に組み込み、昇圧を行うと基板電流がなくなるため、
効率的な昇圧が行えることになる。As shown in FIG. 1, a booster circuit transistor is formed on a Sol substrate. For example, LOCO3 is used for element isolation method.
When this method is used, a transistor with a cross-sectional shape as shown in FIG. 1 is obtained. Then, it becomes completely electrically isolated from the substrate. Therefore, for example, if it is incorporated into a circuit as shown in Figure 2 and boosted, the substrate current will disappear, so
Efficient boosting can be performed.
この発明は、以上説明したように昇圧回路をS0I基板
上に形成することにより、昇圧の効率をあげることがで
きるため外部電源電圧の低電圧化、または昇圧電圧の高
電圧化、または昇圧回路のキャパシタやトランジスタの
数の低減化を行うことが可能となる。As explained above, by forming a booster circuit on an S0I substrate, the efficiency of boosting can be increased. It becomes possible to reduce the number of capacitors and transistors.
第1図は本発明の実施例で用いられるトランジスタの断
面図、第2図は本発明の実施例の回路を示す回路図、第
3図は従来用いられていたトランジスタの断面図である
。FIG. 1 is a sectional view of a transistor used in an embodiment of the present invention, FIG. 2 is a circuit diagram showing a circuit of an embodiment of the invention, and FIG. 3 is a sectional view of a conventionally used transistor.
シリコン基板 酸化膜 素子分M酸化膜 ゲート配線 シリコン 以上 出願人 セイコー電子工業株式会社 代理人 弁理士 林 敬 之 助silicon substrate Oxide film Element M oxide film gate wiring silicon that's all Applicant: Seiko Electronics Industries Co., Ltd. Agent: Patent Attorney Takayoshi Hayashi
昇圧回路の代表的な回路図 第210 Typical circuit diagram of booster circuit 210th
Claims (1)
する半導体装置において、前記トランジスタをSOI基
板上に形成することを特徴とする半導体装置。1. A semiconductor device having a booster circuit that combines a transistor and a capacitor, wherein the transistor is formed on an SOI substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2229475A JPH04109663A (en) | 1990-08-29 | 1990-08-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2229475A JPH04109663A (en) | 1990-08-29 | 1990-08-29 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04109663A true JPH04109663A (en) | 1992-04-10 |
Family
ID=16892762
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2229475A Pending JPH04109663A (en) | 1990-08-29 | 1990-08-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04109663A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0661749A1 (en) * | 1993-12-28 | 1995-07-05 | Seiko Instruments Inc. | Step-up semiconductor integrated circuit and electronic equipment using the semiconductor integrated circuit |
| US5888854A (en) * | 1993-09-27 | 1999-03-30 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a DRAM having an SOI structure |
| US9242535B2 (en) | 2013-09-26 | 2016-01-26 | Aisin Seiki Kabushiki Kaisha | Roof apparatus |
| KR20160091414A (en) | 2014-01-29 | 2016-08-02 | 구로사키 하리마 코포레이션 | Thermal spraying material |
-
1990
- 1990-08-29 JP JP2229475A patent/JPH04109663A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5888854A (en) * | 1993-09-27 | 1999-03-30 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a DRAM having an SOI structure |
| EP0661749A1 (en) * | 1993-12-28 | 1995-07-05 | Seiko Instruments Inc. | Step-up semiconductor integrated circuit and electronic equipment using the semiconductor integrated circuit |
| US9242535B2 (en) | 2013-09-26 | 2016-01-26 | Aisin Seiki Kabushiki Kaisha | Roof apparatus |
| KR20160091414A (en) | 2014-01-29 | 2016-08-02 | 구로사키 하리마 코포레이션 | Thermal spraying material |
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