JPH04115301A - Method and device for interlocking - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a field programmable logic array (F
ield Programmable Logic Ar
ray, FPLA)

[Conventional technology and its issues]

The interlock circuit controls the signal output for arbitrary input signals using a combination signal thereof. Since the interlock conditions change depending on the surrounding conditions of the device using the interlock circuit, many combinations are required.

Conventionally, this was handled by designing a circuit using a relay each time the input conditions of the combination signals changed, or by changing the combination of human input signals by changing the microcomputer software. These methods do not have a degree of freedom regarding the number of input/output signals, require a lot of effort in designing and manufacturing, and changing a circuit that has already been manufactured may have a large impact on other devices, such as changing peripheral devices. The challenge was to give.

SUMMARY OF THE INVENTION An object of the present invention is to provide an interlock method and apparatus that can cope with changes or changes in interlock conditions by simply changing the field programmable logic array without changing other parts.

[Means to solve the problem]

In order to solve the above problems and achieve the above objects, the method of the present invention sets the combined signal input conditions for a plurality of signal inputs as shown in the figure, and inputs this setting signal to the field programmable logic array 1. It is characterized in that the output signal to the subsequent circuit 4 is determined and interlocked.

In order to solve the same problem and achieve the same purpose, the device of the present invention includes an interlock human power condition setting section 2 that sets a combined signal input condition for a plurality of human signal powers as shown in the figure;
A field programmable logic array 1 which inputs the setting signal and determines an output signal to the subsequent circuit 4.
The structure consists of the following.

[For production]

The combined signal input conditions for a plurality of signals are set by the interlock input condition setting section 2, and the setting signals are input to the field programmable logic array 1 to determine the output signal to the subsequent circuit 4. The circuit 4 at the subsequent stage is activated.

〔Example〕

The present invention will be explained in detail below with reference to the drawings.

The drawing is a block diagram showing the configuration of an embodiment of the method and apparatus of the present invention.

The present invention uses a field programmable logic array 1 (FPLA) at the center of an interlock circuit to enable control of arbitrary input/output conditions without changing other peripheral devices.

The configuration of this embodiment shows a case where two output signals are obtained for four signal inputs. The number of output signals is determined by the field programmable logic array 1 used. The conditions set by the interlock manual condition setting section 2 are input to the field programmable logic array 1, and the field programmable logic array 1 outputs the setting signal to the controlled object section 4.

The interlock input condition setting section 2 includes four interlock input condition setting switches A to D, and the interlock input conditions are set by a combination of these switches A to D. That is, the interlock input conditions are set by switches A to D, and the first . Second controlled object X.

An example is shown in which Y is activated when the output signal from the field programmable logic array 1 is at a low level.

In the above configuration, the first controlled object X is the switch A,
It is assumed that the second controlled object Y operates when both switches C and D are closed. This can be expressed as a logical formula as follows.

X=λ・100 ・・・−・・・・・・・・・・・・・
・ (1) Y=go・b ・・・・・・・・・・・・
(2) An interlock circuit is constructed by implementing equations (1) and (2) in the field programmable logic array 1.

That is, when switches A and B are closed, interlock input condition setting section 2 sets the combination signal input condition, and this setting signal is applied to field programmable logic array 1.
The first controlled object X of the controlled object section 4 is actuated by the signal inputted to and outputted from this, and when the switches C and D are similarly closed, the second controlled object Y is actuated.

Interlock conditions can also be easily changed.

For example, if you want to change the operating condition of the first controlled object to when switch A or switch B is closed, you can change the field programmable logic array 1 by changing equation (1) to the following equation (3). , it becomes possible to change the interlock input conditions.

X=λ10 times ・・・・・・・・・・・・・・・・・・
(3) In other words, the interlock circuit can be changed only by changing the field programmable logic array 1 without changing other peripheral circuits, equipment, etc. Therefore, the design and production effort can be significantly reduced. The same applies even if the switch of the manual condition setting section 2 is changed to a signal of the signal input circuit.

In addition to this embodiment, it can be used for opening/closing conditions of electromagnetic valves in semiconductor manufacturing equipment, and the interlock input condition setting section 2 and control target section 4 can also be applied to microcomputers, other peripheral devices, sensors, light emitting diodes, etc. Both positive and negative logic can be used.

〔Effect of the invention〕

As described above, according to the present invention, (1) it is possible to deal with changes or changes in the Zane-Lock conditions by changing only the field programmable logic array without changing other parts (they can be used in common); The design and production effort can be significantly reduced each time the combined signal input conditions change. ■ Zane-Lock input conditions can be easily changed. (2) The number of parts can be reduced compared to circuits using relays, etc. (2) Relays and the like have a short lifespan due to mechanical action, but field programmable logic arrays can be made of semiconductor integrated circuits, so mechanical action can be avoided and the lifespan can be extended.

[Brief explanation of the drawing]

The drawing is a block diagram showing the configuration of an embodiment of the method and apparatus of the present invention. 1...Field programmable logic array, 2-...Interlock input condition setting section, A
. B: Interlock input condition setting switch, 4: Controlled section, X: (1st)
Controlled object, Y... (second) controlled object.

Claims (4)

[Claims] (1) By setting the combined signal input conditions for multiple signal inputs and inputting this setting signal to the field programmable logic array (1), the subsequent circuit (4
) is determined and interlocked. (2) A claim characterized in that the interlock circuit can be changed simply by replacing the field programmable logic array (1) by individually setting output signals for combined signal input conditions of a plurality of signal inputs. The interlock method according to item 1. (3) An interlock input condition setting section (2) that sets the combined signal input conditions for multiple signal inputs, and a field programmable logic that inputs the setting signals and determines the output signal to the subsequent circuit (4). array(
1) An interlock device consisting of: (4) The interlock input condition setting section (2) includes a plurality of interlock input condition setting switches (A, B...) or signal input circuits, and these switches (A, B...
4. The interlock device according to claim 3, wherein the interlock input condition is set by a combination of signals from a signal input circuit or a signal input circuit.